QCLINUX: arm64: dts: qcom: lemans and monaco: Rework RTSS Mailbox DT to use syscon and staging overlays - #1042
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Merge Check Failed: CR Not Eligible for Merge CR 4668089 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Dmitry Baryshkov (@lumag), Ricardo Salveti (@ricardosalveti), Nicolas Dechesne (@ndechesne), Viswanath Kraleti (@vkraleti), Komal Bajaj (@Komal-Bajaj) would you please review the changes. |
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Merge Check Failed: CR Not Eligible for Merge CR 4668089 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Merge Check Failed: CR Not Eligible for Merge CR 4668091 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
Dmitry Baryshkov (lumag)
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Don't spend time on backporting until the change is accepted into -next
…ee overlay" This reverts commit f9e0c59. The original overlay accessed the APSS TCSR mutex/status registers via direct memory-mapped reg ranges and shipped RTSS as a standalone lemans-rtss-mb.dtso overlay. Upstream review feedback on this design requires: - Accessing the TCSR registers via a syscon phandle instead of a direct reg-mapped node. - Folding the RTSS mailbox node into the shared lemans-staging.dtso overlay instead of a separate, RTSS-only DTBO. The following commits reintroduce this support using that syscon-based, staging-overlay design. Signed-off-by: Ram Sargar <rsargar@qti.qualcomm.com>
…ee overlay" This reverts commit 5c6149c. Same as the lemans overlay, the original Monaco overlay accessed the APSS TCSR mutex/status registers via direct memory-mapped reg ranges and shipped RTSS as a standalone monaco-rtss-mb.dtso overlay. Upstream review feedback on this design requires: - Accessing the TCSR registers via a syscon phandle instead of a direct reg-mapped node. - Folding the RTSS mailbox node into the shared monaco-staging.dtso overlay instead of a separate, RTSS-only DTBO. The following commits reintroduce this support using that syscon-based, staging-overlay design. Signed-off-by: Ram Sargar <rsargar@qti.qualcomm.com>
Add DT schema for the Qualcomm APSS Shared Memory Interrupt Notification Unit (apsshm-shared-intu) syscon block. This block is used to trigger doorbell interrupts that notify special event notifications to one or more subsystems such as RTSS. Signed-off-by: Ram Sargar <rsargar@qti.qualcomm.com> (cherry picked from commit bc4441b6380a5cba921bffa9d376d0aca754abc4)
Add the DT schema for the RTSS mailbox, which exposes a shared-memory and IPCC doorbell channel between the application processor and the RTSS subsystem, and manages the boot/suspend handshake with RTSS. Signed-off-by: Ram Sargar <rsargar@qti.qualcomm.com> (cherry picked from commit 746c85e2b945cda030f5f10041cc6d6643b3c740)
… Mailbox Add ipcc1-4 mailbox nodes, widen the tcsr syscon's reg range to cover both TCSR request/response registers, and add the apss_shared_ipc syscon node for the Lemans platform. These back the syscon/mbox phandle references used by the Lemans RTSS mailbox node (qcom,rtss-mailbox). Signed-off-by: Ram Sargar <rsargar@qti.qualcomm.com> (cherry picked from commit 495968715f30bf12e50ea71adf1b7db9ffd3c750)
Add the rtss_mailbox overlay node for the Lemans platform, using ipcc1-ipcc4 and the tcsr/apss_shared_ipc syscon nodes. Place it under &soc, alongside the other simple-bus child nodes in this file. Signed-off-by: Ram Sargar <rsargar@qti.qualcomm.com> (cherry picked from commit ffc450f489ed42d2c383ccd419c0757398ee8d23)
… for RTSS Mailbox Add ipcc1-4 mailbox nodes, widen the tcsr syscon's reg range to cover both TCSR request/response registers, and add the apss_shared_ipc syscon node for the Monaco platform. These back the syscon/mbox phandle references used by the Monaco RTSS mailbox node (qcom,rtss-mailbox). Reserve the memory regions used by the SAIL/RTSS subsystem for its TZ mailbox, shared-memory mailbox, and OTA buffer on Monaco. These regions back the memory-region references used by the Monaco RTSS mailbox node. Signed-off-by: Ram Sargar <rsargar@qti.qualcomm.com> (cherry picked from commit e8cda0f46a9713e3dc91280f8aff212b610f9311)
Add the rtss_mailbox overlay node for the Monaco platform, mirroring the Lemans RTSS mailbox node. Place it under &soc, alongside the other simple-bus child nodes in this file. Signed-off-by: Ram Sargar <rsargar@qti.qualcomm.com> (cherry picked from commit 3ae6ea8d823ba9fa2764b762323d9318921c52d1)
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Merge Check Failed: CR Not Eligible for Merge CR 4668068 is not eligible for merge. The parent software image for kernel.qli.2.0 is not development complete. Entity: Please ensure the CR passes both CCT (ComponentChangeTasks) and ICT (Integration Change Tasks) validations. |
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Thank you, Shiraz Hashim (@shashim-quic), for the quick approval. Dmitry Baryshkov (@lumag), Ricardo Salveti (@ricardosalveti), Viswanath Kraleti (@vkraleti), Komal Bajaj (@Komal-Bajaj), could you please provide your approval as well to help unblock this PR? |
Test Matrix
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Salendarsingh Gaud (sgaud-quic)
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Crash on 8300-ride :
https://lava-oss.qualcomm.com/scheduler/job/244503
[ 2.092471][ T1] Internal error: synchronous external abort: 0000000096000010 [#1] SMP
[ 2.100952][ T1] Modules linked in:
[ 2.104806][ T1] CPU: 3 UID: 0 PID: 1 Comm: swapper/0 Tainted: G S M 6.18.44-g96841104b8c7 #1 PREEMPT
[ 2.115956][ T1] Tainted: [S]=CPU_OUT_OF_SPEC, [M]=MACHINE_CHECK
[ 2.122389][ T1] Hardware name: Qualcomm Technologies, Inc. QCS8300 Ride (DT)
[ 2.129973][ T1] pstate: 80000005 (Nzcv daif -PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 2.137823][ T1] pc : qcom_ipcc_probe+0x84/0x410
[ 2.142838][ T1] lr : qcom_ipcc_probe+0x68/0x410
[ 2.147848][ T1] sp : ffff800082c3b840
[ 2.151964][ T1] x29: ffff800082c3b8b0 x28: ffff80008260b010 x27: ffff800081add260
[ 2.159994][ T1] x26: ffff000a01c32810 x25: ffff000a017b1c10 x24: ffff000efe83c500
[ 2.168023][ T1] x23: 0000000000000000 x22: ffff000a01c38280 x21: ffff800080b0cd4c
[ 2.176052][ T1] x20: ffff000a01c32800 x19: ffff800082c55008 x18: 00000000ffffffff
[ 2.184082][ T1] x17: ffff000a00361a00 x16: ffff000a00361400 x15: ffff800082c3b570
[ 2.192110][ T1] x14: 0000000000000000 x13: ffff000a00f30498 x12: 0000000000000000
[ 2.200140][ T1] x11: ffff800082c55fff x10: fffffffffffff000 x9 : ffff80008127f434
[ 2.208169][ T1] x8 : ffff800082c3b648 x7 : 0000000000000000 x6 : 0000000000000001
[ 2.216199][ T1] x5 : ffff80008260b000 x4 : ffff80008260b310 x3 : 0000000000000000
[ 2.224229][ T1] x2 : ffff000a00908040 x1 : ffff000a00908040 x0 : ffff800082c55000
[ 2.232259][ T1] Call trace:
[ 2.235484][ T1] qcom_ipcc_probe+0x84/0x410 (P)
[ 2.240494][ T1] platform_probe+0x64/0xa8
[ 2.244970][ T1] really_probe+0xc8/0x3a0
[ 2.249356][ T1] __driver_probe_device+0x8c/0x1b0
[ 2.254545][ T1] driver_probe_device+0x44/0x120
[ 2.259554][ T1] __device_attach_driver+0xc4/0x168
[ 2.264831][ T1] bus_for_each_drv+0x90/0xf8
[ 2.269484][ T1] __device_attach+0xa8/0x1c8
[ 2.274136][ T1] device_initial_probe+0x1c/0x30
[ 2.279145][ T1] bus_probe_device+0xb4/0xc0
[ 2.283797][ T1] device_add+0x500/0x718
[ 2.288092][ T1] of_device_add+0x4c/0x70
[ 2.292480][ T1] of_platform_device_create_pdata+0x9c/0x158
[ 2.298558][ T1] of_platform_bus_create+0x194/0x380
[ 2.303924][ T1] of_platform_bus_create+0x1f8/0x380
[ 2.309290][ T1] of_platform_populate+0x84/0x170
[ 2.314388][ T1] of_platform_default_populate_init+0xf8/0x118
[ 2.320647][ T1] do_one_initcall+0x60/0x2c0
[ 2.325301][ T1] do_initcalls+0xfc/0x1f8
[ 2.329687][ T1] kernel_init_freeable+0x13c/0x298
[ 2.334875][ T1] kernel_init+0x2c/0x1f8
[ 2.339173][ T1] ret_from_fork+0x10/0x20
[ 2.343561][ T1] Code: 54000f68 91002013 a90a63f7 d503201f (b9400277)
[ 2.350532][ T1] ---[ end trace 0000000000000000 ]---
[ 2.355987][ T1] Kernel panic - not syncing: synchronous external abort: Fatal exception
[ 2.364551][ T1] SMP: stopping secondary CPUs
[ 2.369473][ T1] Reboot failed -- System halted
let me check Salendarsingh Gaud (@sgaud-quic). |
IQ8 - NHLOS AC policy update is missing, we can hold on until further update |
Target milestone: QLI-2.1
Summary
Backport of qualcomm-linux/kernel-topics#1768 to qcom-6.18.y for
QLI 2.1-RC
Reworks the RTSS Mailbox device-tree support on Lemans and Monaco to
address maintainers review feedback on the original design merged via
#675: syscon-based TCSR access, staging-overlay consolidation, and
removal of the standalone RTSS-only DTBOs.
Impact
time for configs that include the staging overlay, per the existing FIT config).
Unchanged
Tracking issue
qualcomm-linux/meta-qcom#3085
This PR dependency
Testing
Change Request
CRs-Fixed: 4668089
RTSS Feature Enablement Exception
https://jira-dc.qualcomm.com/jira/browse/QLIJIRA-123