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soumajit-m/README.md

Hi, I'm Soumajit Mandal 👋

Undergrad @ IIEST Shibpur • Incoming Hardware Intern (DFT) @ Texas Instruments
Digital IC Design • Design for Testability (DFT) • Computer Architecture • ML for EDA

LinkedIn Email GitHub

🚀 Highlights

  • 💼 Digital Design Hardware Intern (DFT Team) at Texas Instruments — Automated Cadence DFT flow (Genus, Modus, Xcelium), VCD parsing & XGBoost toggle modeling to mitigate peak scan $IR$-drop.
  • ⚙️ Processor Architectures: Cycle-accurate Intel 8085 RTL (246 instructions, bus demux, interrupt hooks) & Intel 8086 (BIU with segmentation, prefetch queue, EU ALU).
  • ⚡ Hardware Acceleration: Parameterized 2D Systolic Array MAC accelerator with output-stationary dataflow in Verilog.
  • 🔬 ML for EDA: 2D U-Net CNN on CircuitNet predicting routing congestion & $IR$-drop from early placement layouts.

🛠️ Skills & Toolchain

  • EDA & Hardware: Cadence (Genus, Modus, Xcelium), Xilinx Vivado, GTKWave, Verilog, SystemVerilog
  • DFT & Timing: Scan Insertion/Stitching, Fullscan, OPMISR, Lock-up Latches, SAF/TDF/$I_{DDQ}$, Gate-Level Sim, STA, VCD Profiling
  • Languages & Frameworks: Python, C++, Perl, Tcl, Bash, Git, Linux, PyTorch, XGBoost, Scikit-Learn

📊 GitHub Activity

GitHub Stats Top Languages

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  1. 8085-microprocessor-rtl 8085-microprocessor-rtl Public

    A cycle-accurate Verilog RTL core of the classic Intel 8085 microprocessor, featuring complete instruction set support and authentic hardware bus multiplexing.

    Verilog

  2. 8086-pipelined-core-verilog 8086-pipelined-core-verilog Public

    Synthesizable Intel 8086 pipelined core in Verilog with decoupled BIU/EU, 6-byte prefetch FIFO, 20-bit segmentation, and Artix-7 FPGA synthesis.

    Verilog

  3. systolic-mac-accelerator systolic-mac-accelerator Public

    Parameterized 2D Systolic MAC Array for matrix multiplication in Verilog-2001. Features nearest-neighbor dataflow, skew buffers, and 100 MHz timing on Artix-7.

    Verilog

  4. circuitnet-congestion-predictor circuitnet-congestion-predictor Public

    Multi-Task Attention U-Net for VLSI routing congestion & dynamic IR drop co-estimation using CircuitNet 5-channel standard on RISC-V macros, built in PyTorch.

    Python

  5. cpp-cpu-raytracer cpp-cpu-raytracer Public

    High-performance CPU/GPU Ray Tracer built in C++

    C++

  6. sm-portfolio sm-portfolio Public

    Welcome to my 3D Portfolio! This interactive web experience showcases my skills, projects, and achievements using cutting-edge web technologies and 3D graphics.

    TypeScript