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Move ARM64 JIT templates to read-only data on FreeBSD and OpenBSD - #364

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selsta:bsd-arm64-jit-xonly

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@selsta selsta commented Oct 18, 2026

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The templates are copied into a separate JIT allocation and are never executed in place. Keep them in .rodata on FreeBSD and OpenBSD so the source bytes remain readable without requiring executable storage.

This fixes JIT construction on OpenBSD arm64, where .text is execute-only.

The templates are copied into a separate JIT allocation and are never
executed in place. Keep them in .rodata on FreeBSD and OpenBSD so the
source bytes remain readable without requiring executable storage.

This fixes JIT construction on OpenBSD arm64, where .text is execute-only.
@selsta

selsta commented Oct 18, 2026 •

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#363 is more generic and the better solution here.

@selsta selsta closed this Oct 18, 2026
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selsta deleted the bsd-arm64-jit-xonly branch October 18, 2026 22:44
thomasbuilds pushed a commit to thomasbuilds/RandomX that referenced this pull request Oct 22, 2026
PR tevador#350 showed that the audit had not reviewed upstream's closed pull
requests and issues. They were reviewed (tevador#300-tevador#364 and the recent
issues) and the results are in AUDIT_v2_2026-10.md section 8:

- tevador#352: the maintainers acknowledged C-F6 (RISC-V soft-AES index 255 at
  VLEN >= 2048) and declined a per-instruction mask; C-F6 now records
  this, and the recommendation is a one-time VLEN check.
- tevador#336: a maintainer argued against describing the SuperscalarHash
  generator in full in the docs; ALG-7 and recommendation 4 now say that
  chapter 6.4 is a proposal and name the alternative.
- The same external review found three wrong comments, fixed here: the
  x86 v2 light-mode template modifies "ma", not "mx"; the RISC-V vector
  light-mode loop updates mp; v17 is clobbered by vfwcvt into v16.
- Upstream's v1.x branch (9b012ab), which Monero runs until the v2 fork,
  has B-1 and most of the Low fixes. B-1 reproduces there under
  qemu-aarch64: 6/6 wrong light-mode JIT hashes with the round 1 proof of
  concept, 0/6 with the patch.

Also corrected in the report's bottom line: the large-page leak (E-4)
only affected sizes that are not a multiple of the huge page size, and
C-F1/C-F2 are not v1-era (they are in the 2026 RISC-V vector JIT).

Comment-only code changes; the x86-64 and riscv64 (GCC 14) suites pass.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01Mj5ZB66Pd5vxCkgehReFDs
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