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Fix misaligned light-mode data loads in the RISC-V vector JIT - #367
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SChernykh merged 1 commit intoOct 25, 2026
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Oct 25, 2026
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randomx_riscv64_vector_program_main_loop_light_mode_dataholds two 8-byte words that the light-mode loop reads withldon every iteration. Nothing aligns them, and they end up misaligned, so each light-mode hash does 32,768 misaligned loads. On RISC-V cores without hardware support for misaligned access these trap and are either emulated (slow) or raise SIGBUS.