Adding NUCLEO-G474RE

.cmsis/Trace+NUCLEO-G474RE.dbgconf

@@ -0,0 +1,64 @@
+// File: STM32G4xx.dbgconf
+// Version: 1.0.1
+// Note: refer to STM32G4xx Reference manual (RM0440)
+//       refer to STM32G4xx datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug MCU configuration register (DBGMCU_CR)
+//   <o.2>  DBG_STANDBY              <i> Debug Standby mode
+//   <o.1>  DBG_STOP                 <i> Debug Stop mode
+//   <o.0>  DBG_SLEEP                <i> Debug Sleep mode
+// </h>
+DbgMCU_CR = 0x00000007;
+
+// <h> Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1)
+//                                   <i> Reserved bits must be kept at reset value
+//   <o.31> DBG_LPTIM1_STOP          <i> LPTIM1 counter stopped when core is halted
+//   <o.30> DBG_I2C3_STOP            <i> I2C3 SMBUS timeout counter stopped when core is halted
+//   <o.22> DBG_I2C2_STOP            <i> I2C2 SMBUS timeout counter stopped when core is halted
+//   <o.21> DBG_I2C1_STOP            <i> I2C1 SMBUS timeout counter stopped when core is halted
+//   <o.12> DBG_IWDG_STOP            <i> Independent watchdog counter stopped when core is halted
+//   <o.11> DBG_WWDG_STOP            <i> Window watchdog counter stopped when core is halted
+//   <o.10> DBG_RTC_STOP             <i> RTC counter stopped when core is halted
+//   <o.5>  DBG_TIM7_STOP            <i> TIM7 counter stopped when core is halted
+//   <o.4>  DBG_TIM6_STOP            <i> TIM6 counter stopped when core is halted
+//   <o.3>  DBG_TIM5_STOP            <i> TIM5 counter stopped when core is halted
+//   <o.2>  DBG_TIM4_STOP            <i> TIM4 counter stopped when core is halted
+//   <o.1>  DBG_TIM3_STOP            <i> TIM3 counter stopped when core is halted
+//   <o.0>  DBG_TIM2_STOP            <i> TIM2 counter stopped when core is halted
+// </h>
+DbgMCU_APB1_Fz1 = 0x00000000;
+
+// <h> Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
+//                                   <i> Reserved bits must be kept at reset value
+//   <o.1>  DBG_I2C4_STOP            <i> I2C4 SMBUS timeout counter stopped when core is halted
+// </h>
+DbgMCU_APB1_Fz2 = 0x00000000;
+
+// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
+//                                   <i> Reserved bits must be kept at reset value
+//   <o.26> DBG_HRTIM_STOP           <i> HRTIM counter stopped when core is halted
+//   <o.20> DBG_TIM20_STOP           <i> TIM20 counter stopped when core is halted
+//   <o.18> DBG_TIM17_STOP           <i> TIM17 counter stopped when core is halted
+//   <o.17> DBG_TIM16_STOP           <i> TIM16 counter stopped when core is halted
+//   <o.16> DBG_TIM15_STOP           <i> TIM15 counter stopped when core is halted
+//   <o.13> DBG_TIM8_STOP            <i> TIM8 counter stopped when core is halted
+//   <o.11> DBG_TIM1_STOP            <i> TIM1 counter stopped when core is halted
+// </h>
+DbgMCU_APB2_Fz = 0x00000000;
+
+// <h> TPIU Pin Routing
+//   <i> TRACECLK: Pin PE2
+//   <i> TRACED[0]: Pin PE3
+//   <i> TRACED[1]: Pin PE4
+//   <i> TRACED[2]: Pin PE5
+//   <i> TRACED[3]: Pin PE6
+// </h>
+
+// <h> Flash Download Options
+//   <o.0> Option Byte Loading      <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
+// </h>
+DoOptionByteLoading = 0x00000000;
+
+// <<< end of configuration section >>>

.cmsis/Trace+NUCLEO-G474RE.dbgconf.base@0.0.0

@@ -0,0 +1,64 @@
+// File: STM32G4xx.dbgconf
+// Version: 1.0.1
+// Note: refer to STM32G4xx Reference manual (RM0440)
+//       refer to STM32G4xx datasheets
+
+// <<< Use Configuration Wizard in Context Menu >>>
+
+// <h> Debug MCU configuration register (DBGMCU_CR)
+//   <o.2>  DBG_STANDBY              <i> Debug Standby mode
+//   <o.1>  DBG_STOP                 <i> Debug Stop mode
+//   <o.0>  DBG_SLEEP                <i> Debug Sleep mode
+// </h>
+DbgMCU_CR = 0x00000007;
+
+// <h> Debug MCU APB1 freeze register1 (DBGMCU_APB1FZR1)
+//                                   <i> Reserved bits must be kept at reset value
+//   <o.31> DBG_LPTIM1_STOP          <i> LPTIM1 counter stopped when core is halted
+//   <o.30> DBG_I2C3_STOP            <i> I2C3 SMBUS timeout counter stopped when core is halted
+//   <o.22> DBG_I2C2_STOP            <i> I2C2 SMBUS timeout counter stopped when core is halted
+//   <o.21> DBG_I2C1_STOP            <i> I2C1 SMBUS timeout counter stopped when core is halted
+//   <o.12> DBG_IWDG_STOP            <i> Independent watchdog counter stopped when core is halted
+//   <o.11> DBG_WWDG_STOP            <i> Window watchdog counter stopped when core is halted
+//   <o.10> DBG_RTC_STOP             <i> RTC counter stopped when core is halted
+//   <o.5>  DBG_TIM7_STOP            <i> TIM7 counter stopped when core is halted
+//   <o.4>  DBG_TIM6_STOP            <i> TIM6 counter stopped when core is halted
+//   <o.3>  DBG_TIM5_STOP            <i> TIM5 counter stopped when core is halted
+//   <o.2>  DBG_TIM4_STOP            <i> TIM4 counter stopped when core is halted
+//   <o.1>  DBG_TIM3_STOP            <i> TIM3 counter stopped when core is halted
+//   <o.0>  DBG_TIM2_STOP            <i> TIM2 counter stopped when core is halted
+// </h>
+DbgMCU_APB1_Fz1 = 0x00000000;
+
+// <h> Debug MCU APB1 freeze register 2 (DBGMCU_APB1FZR2)
+//                                   <i> Reserved bits must be kept at reset value
+//   <o.1>  DBG_I2C4_STOP            <i> I2C4 SMBUS timeout counter stopped when core is halted
+// </h>
+DbgMCU_APB1_Fz2 = 0x00000000;
+
+// <h> Debug MCU APB2 freeze register (DBGMCU_APB2FZR)
+//                                   <i> Reserved bits must be kept at reset value
+//   <o.26> DBG_HRTIM_STOP           <i> HRTIM counter stopped when core is halted
+//   <o.20> DBG_TIM20_STOP           <i> TIM20 counter stopped when core is halted
+//   <o.18> DBG_TIM17_STOP           <i> TIM17 counter stopped when core is halted
+//   <o.17> DBG_TIM16_STOP           <i> TIM16 counter stopped when core is halted
+//   <o.16> DBG_TIM15_STOP           <i> TIM15 counter stopped when core is halted
+//   <o.13> DBG_TIM8_STOP            <i> TIM8 counter stopped when core is halted
+//   <o.11> DBG_TIM1_STOP            <i> TIM1 counter stopped when core is halted
+// </h>
+DbgMCU_APB2_Fz = 0x00000000;
+
+// <h> TPIU Pin Routing
+//   <i> TRACECLK: Pin PE2
+//   <i> TRACED[0]: Pin PE3
+//   <i> TRACED[1]: Pin PE4
+//   <i> TRACED[2]: Pin PE5
+//   <i> TRACED[3]: Pin PE6
+// </h>
+
+// <h> Flash Download Options
+//   <o.0> Option Byte Loading      <i> Launch the Option Byte Loading after a Flash Download by setting the OBL_LAUNCH bit (causes a reset)
+// </h>
+DoOptionByteLoading = 0x00000000;
+
+// <<< end of configuration section >>>

.cmsis/Trace+NUCLEO-G474RE@STLink.ctrace.yml

@@ -0,0 +1,25 @@
+# Trace sources are owned by this file and the CMSIS Trace Configuration dialog.
+# Addresses are resolved from the selected ELF; do not hard-code SRAM addresses.
+ctrace:
+  setup:
+    - core: Cortex-M4
+      timestamps:
+        clock: 16000000
+        itm-prescaler: 1
+      data:
+        - location: g_trace_sine
+          label: Sine
+          access: W
+          size: 4
+          output: value
+        - location: g_trace_noise
+          label: Noise
+          access: W
+          size: 4
+          output: value
+      itm:
+        enable: 0x00000002
+      pcsampling:
+        period: 16384
+      synchronization:
+        DWT: 16M

.cmsis/Trace+NUCLEO-G474RE@ULINKplus.ctrace.yml

@@ -0,0 +1,25 @@
+# Trace sources are owned by this file and the CMSIS Trace Configuration dialog.
+# Addresses are resolved from the selected ELF; do not hard-code SRAM addresses.
+ctrace:
+  setup:
+    - core: Cortex-M4
+      timestamps:
+        clock: 16000000
+        itm-prescaler: 1
+      data:
+        - location: g_trace_sine
+          label: Sine
+          access: W
+          size: 4
+          output: value
+        - location: g_trace_noise
+          label: Noise
+          access: W
+          size: 4
+          output: value
+      itm:
+        enable: 0x00000002
+      pcsampling:
+        period: 8192
+      synchronization:
+        DWT: 16M

Board/NUCLEO-G474RE/Board.clayer.yml

@@ -0,0 +1,30 @@
+layer:
+  type: Board
+  description: Minimal CMSIS device support for NUCLEO-G474RE
+  for-device: STM32G474RETx
+
+  packs:
+    - pack: Keil::STM32G4xx_DFP@2.0.0
+
+  define:
+    - STM32G474xx
+    - CMSIS_device_header: '"stm32g4xx.h"'
+    - USER_VECT_TAB_ADDRESS
+
+  add-path:
+    - ../../ThirdParty/ST/cmsis-device-g4/Include
+
+  groups:
+    - group: Board
+      files:
+        - file: main.c
+        - file: target.c
+    - group: CMSIS Device
+      files:
+        - file: ../../ThirdParty/ST/cmsis-device-g4/Source/Templates/gcc/startup_stm32g474xx.s
+        - file: ../../ThirdParty/ST/cmsis-device-g4/Source/Templates/system_stm32g4xx.c
+
+  linker:
+    - script: ../Support/gcc_linker_script.ld.src
+      regions: regions.h
+      for-compiler: GCC

Board/NUCLEO-G474RE/README.md

@@ -0,0 +1,21 @@
+# NUCLEO-G474RE
+
+Local layer for `STMicroelectronics::STM32G474RETx`, Cortex-M4.
+
+| Setting | Local configuration |
+| --- | --- |
+| DFP | `Keil::STM32G4xx_DFP@2.0.0` |
+| ST startup/system | `startup_stm32g474xx.s`, `system_stm32g4xx.c` |
+| Linked Flash | 512 KiB at `0x08000000` |
+| Linked SRAM | 128 KiB at `0x20000000` |
+| Main stack | 4 KiB |
+| Nominal reset clock | 16 MHz HSI |
+| Debugger sets | `ULINKplus`, `STLink`; same firmware, SWD / 1 Mbaud SWO |
+
+The layer follows the [shared board design](../../docs/BOARD_SUPPORT.md#shared-layer-design).
+DFP sequences provide the PB3 SWO pin/clock setup; no local sequence override
+is used. Follow the [G474 wiring table](../../docs/ST_BOARD_BRINGUP.md#nucleo-g474re--mb1367)
+for connector, jumper and power settings.
+
+Hardware trace validation is pending; see [Validation](../../docs/VALIDATION.md)
+and [debugger profiles](../../docs/DEBUG_PROBES.md) for capture setup.

Board/NUCLEO-G474RE/main.c

@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+#include "app.h"
+#include "target.h"
+
+int main(void) {
+  target_init();
+  (void)app_main();
+  for (;;) {
+    /* app_main returns only when RTX5 startup fails. */
+  }
+}

Board/NUCLEO-G474RE/regions.h

@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/* Memory selected from Keil::STM32G4xx_DFP@2.0.0, STM32G474RETx.
+ * Use one internal Flash region and one SRAM region for this baseline.
+ * Additional banks and external memory are deliberately not linked yet.
+ */
+#ifndef TRACE_MEMORY_REGIONS_H
+#define TRACE_MEMORY_REGIONS_H
+
+#define __ROM0_BASE 0x08000000
+#define __ROM0_SIZE 0x00080000
+#define __RAM0_BASE 0x20000000
+#define __RAM0_SIZE 0x00020000
+#define __STACK_SIZE 0x00001000
+#define __HEAP_SIZE 0x00000000
+
+#endif

Board/NUCLEO-G474RE/target.c

@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+#include CMSIS_device_header
+#include "target.h"
+
+void target_init(void) {
+  /* Vendor SystemInit has run. Retain the internal-oscillator baseline. */
+  SystemCoreClockUpdate();
+}
+
+uint32_t target_core_clock_hz(void) { return SystemCoreClock; }

README.md

@@ -5,8 +5,8 @@ architecture across a selection of boards and trace use cases. It is not a board
 bring-up project or a reference example, and is currently not intended as a
 starting point for customer projects.
 
-A common firmware baseline for testing trace across Cortex-M boards and debug
-probes. One **CMSIS solution** builds a shared **RTX5 application** through eight
+ A common firmware baseline for testing trace across Cortex-M boards and debug
+ probes. One **CMSIS solution** builds a shared **RTX5 application** through eight
 local board layers, covering Cortex-M4, Cortex-M7 and Cortex-M33.
 
 The workload updates sine and deterministic-noise variables every 100 ms for DWT
@@ -27,6 +27,7 @@ Capture-start and pause/end recording issues remain; see [Validation](docs/VALID
 | [MCBSTM32F400](Board/MCBSTM32F400/README.md) | Cortex-M4 | `ULINKplus` |
 | [NUCLEO-L552ZE-Q](Board/NUCLEO-L552ZE-Q/README.md) | Cortex-M33, TrustZone off | `ULINKplus`, `STLink` |
 | [NUCLEO-F756ZG](Board/NUCLEO-F756ZG/README.md) | Cortex-M7 | `ULINKplus`, `STLink` |
+| [NUCLEO-G474RE](Board/NUCLEO-G474RE/README.md) | Cortex-M4 | `ULINKplus`, `STLink` |
 | [STM32F429I-DISCO](Board/STM32F429I-DISCO/README.md) | Cortex-M4 | `ULINKplus`, `STLink` |
 | [NUCLEO-F401RE](Board/NUCLEO-F401RE/README.md) | Cortex-M4 | `ULINKplus`, `STLink` |
 | [NUCLEO-F446RE](Board/NUCLEO-F446RE/README.md) | Cortex-M4 | `STLink` |

ThirdParty/README.md

@@ -8,11 +8,12 @@ HAL/LL or a complete Cube firmware package.
 | --- | --- | --- |
 | [cmsis-device-f4](https://github.com/STMicroelectronics/cmsis-device-f4/tree/v2.6.11) | v2.6.11 | [Apache-2.0](ST/cmsis-device-f4/LICENSE.md) |
 | [cmsis-device-f7](https://github.com/STMicroelectronics/cmsis-device-f7/tree/v1.2.10) | v1.2.10 | [Apache-2.0](ST/cmsis-device-f7/LICENSE.md) |
+| [cmsis-device-g4](https://github.com/STMicroelectronics/cmsis-device-g4/tree/v1.2.6) | v1.2.6 | [Apache-2.0](ST/cmsis-device-g4/LICENSE.md) |
 | [cmsis-device-l5](https://github.com/STMicroelectronics/cmsis-device-l5/tree/v1.0.7) | v1.0.7 | [Apache-2.0](ST/cmsis-device-l5/LICENSE.md) |
 | [cmsis-device-h7](https://github.com/STMicroelectronics/cmsis-device-h7/tree/v1.10.7) | v1.10.7 | [Apache-2.0](ST/cmsis-device-h7/LICENSE.md) |
 
 [ST/sources.json](ST/sources.json) records immutable commits, selected paths,
-SHA256 hashes and byte counts for all 30 files: licenses, family/device headers,
+SHA256 hashes and byte counts for all 34 files: licenses, family/device headers,
 GNU startup assembly and system templates. Other devices referenced by the
 umbrella headers are intentionally absent.