5-stage-pipelined-processor

Here are 11 public repositories matching this topic...

kerimturak / level-v

LEVEL: Open-source RV32IMC RISC-V processor core with pipelined microarchitecture, cache support, SoC peripherals and verification framework.

Updated Jul 6, 2026
SystemVerilog

arhamhashmi01 / rv32i-pipeline-processor

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This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

vhdl verilog microprocessor vivado hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator rv32im asic-design chip-design 5-stage-pipelined-processor rv32i-processor

Updated Feb 19, 2025
Verilog

akira2963753 / mips-5stage-cpu

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This is NTUST-EE 2025 Computer Organization, the course's final project is the implementation of the 5-stage pipelined cpu based on mips.

cpu mips-processor mips-cpu computer-organisation-architechure 5-stage-pipelined-processor

Updated Mar 16, 2026
Verilog

arhamhashmi01 / rv32i-sv

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This repository contain the implementation of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on System Verilog

microprocessor systemverilog hardware-designs risc-v rv32i systemverilog-hdl 5-stage-pipeline 5-stage-pipelined-processor

Updated Jun 10, 2024
SystemVerilog

Ali-975 / rv32i-5-stage-pipelined-processor

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RISC-V RV32I 5-stage pipelined processor implemented in SystemVerilog with RTL design, testbench, and hex-based instruction memory.

data-flow riscv stages control-hazards data-hazards 5-stage-pipelined-processor rv32i-processor

Updated Sep 13, 2025
SystemVerilog

Mahekkumar-Varasada / 5-Stage-MIPS-Pipelined-with-Hazard-Mitigation

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The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.

mips computer-architecture hazard-detection mips-architecture mips32 nirma-university forwarding-unit control-hazards 5-stage-pipelined-processor hazard-mitigation

Updated Oct 27, 2024
Verilog

poojith06 / riscv-pipeline-processor

Star

A 5-stage pipelined RISC-V processor implemented in Verilog with hazard detection unit and data forwarding.

processor-architecture processor verilog pipeline-processor risc-v rv64i 5-stage-pipelined-processor

Updated Mar 19, 2026
Verilog

Ammar-Bin-Amir / RV32I_5-Stage_Pipelined_CPU

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Processor Design of RV32I 5-Stage Pipelined CPU

risc-v rv32i digital-circuit-design rtl-design single-cycle-processor 5-stage-pipelined-processor

Updated Jul 4, 2024
SystemVerilog

Brunomvsilva / VESPA-SoC

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A custom 5-stage pipelined CPU implemented on FPGA and based on the VeSPA ISA, designed for educational exploration of computer architecture and digital design.

fpga verilog soc-design 5-stage-pipelined-processor vespa-isa

Updated Nov 26, 2025
Verilog

ShogunYash / OlympusPipeliner

Star

A CPU Simulator

simulator cpu cpp forwarding risc-v pipeline-cpu ripes 5-stage-pipelined-processor

Updated Mar 27, 2025
C++

narenhalubai / 32bit-5-Stage-Pipelined-RISC-Processor

Star

This project is a simple 32-bit pipelined RISC processor built in Verilog. It is based on a MIPS-style architecture and is divided into the five classic pipeline stages: fetch, decode, execute, memory, and write-back. The processor can run basic instructions like addition and memory operations, and the waveform simulation shows how an instruction

processor waveform verilog alu risc 5 32-bit pipelined-processor 5-stage-pipelined-processor

Updated Jun 5, 2026
Verilog

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