fips-197

AES-128 IP core in SystemVerilog. FIPS-197 compliant, dual-licensed, with secure (DPA-resistant) and pipelined variants.

AES block cipher (128/192/256-bit) built from scratch in Java, following the NIST FIPS-197 spec with per-round state tracing

AES-256 from FIPS-197 in Lean 4: test vectors, decrypt∘encrypt = id, S-box uniformity 4 and nonlinearity 112, branch number 5, ≥25 active S-boxes in any 4 rounds. Kernel-checked, re-checked by Tenet.

Implementation of the AES cryptography standard [FIPS 197] and other block cipher modes from NIST SP 800-38X.

AES-128 in ECB mode.

AES-128 from scratch in Python: FIPS 197 core, CBC + HMAC authenticated encryption, validated against NIST test vectors

AES (FIPS-197 / Rijndael) implementation in Java with 128/192/256-bit keys and full key schedule.

AES-256 FPGA IP core in SystemVerilog. FIPS-197 compliant, NIST-validated, dual-licensed.

Browser-based AEGIS-256 authenticated encryption demo (draft-irtf-cfrg-aegis-aead-18). AES round function, 6-state sponge update, and tag derivation implemented from scratch and verified against official test vectors.