high-speed-arithmetic

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bdivya-9125 / Comparative-Study-of-16bit-Adder-Architectures

Design and simulation of 16-bit Ripple Carry and Weinberger Adders using Cadence Virtuoso. Includes full adder modeling, schematic creation, waveform analysis, and detailed delay-power comparison.

vlsi cadence digital-design waveform-analysis cmos-technology ripple-carry-adder eda-tools gpdk180 schematic-design adder-architecture weinberger-adder vlsi-simulation high-speed-arithmetic

Updated Dec 7, 2025

KARAN-D05 / High-Performance-Multipliers

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RTL implementations of high-performance 32-Bit multiplier architectures, exploring arithmetic datapaths, synthesis, timing analysis, PPA trade-offs with post-synthesis GLS and characterization of impact of carry-propagation architectures on multipliers performance. 🔢.

computer-arithmetic high-speed-arithmetic high-performance-architectures performance-power-area

Updated Sep 20, 2026
SystemVerilog

KARAN-D05 / High-Performance-Adder-Architectures

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RTL implementations of high-performance 64-Bit adder architectures, exploring carry computation, synthesis, timing analysis, and PPA trade-offs with post synthesis GLS with selected architectures taken to GDSII 🔢.

design-space-exploration computer-arithmetic high-speed-arithmetic parallel-prefix-adders high-performance-architectures performance-power-area

Updated Sep 17, 2026
SystemVerilog

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