Quick Verilog Module Isolator - Isolates a design for testing.
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Updated
Dec 11, 2018 - Verilog
Quick Verilog Module Isolator - Isolates a design for testing.
VHDL SPI master on FPGA controlling ADMV1013/ADMV1014 microwave up/down converters
A SystemVerilog-based UART (Universal Asynchronous Receiver/Transmitter) module built from scratch using FSM design. Includes baud tick generator, transmitter and receiver FSMs, and simulation testbenches for 8N1 serial communication.
Finite state machine (FSM) design in VHDL — simulated and implemented on FPGA hardware with Intel Quartus. University project, HsH.
Verilog-2001 & FPGA Linter aligned with Google's Verilog Style Guide.
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