Build software better, together

os-fpga / Virtual-FPGA-Lab

This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.

open-source os gsoc tl-verilog makerchip virtual-fpga

Updated Apr 25, 2026
TL-Verilog

ShonTaware / RISC-V_Core_4_Stage

Star

RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set

riscv isa tl-verilog makerchip risc-vcore

Updated Jan 14, 2021

AnoushkaTripathi / NASSCOM-RISC-V-based-MYTH-program

Star

Learn digital logic design from basics to pipelines using TL-Verilog and Makerchip — fast, practical, and beginner-friendly! 🚀

risc-v tl-verilog makerchip

Updated Apr 2, 2025

ninja3011 / riscv-cpu-core

Star

A pipelined RISC-V CPU Core Implemented in Makerchip using TL-Verilog

gnu-toolchain risc-v circuit-design tl-verilog makerchip

Updated Mar 4, 2022

ChaminduS / Building-a-RISC-V-CPU-Core

Star

This repository contains my work in completing the course titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX.

risc-v digital-logic-design cpu-design makerchip

Updated Apr 25, 2021

RISCV-MYTH-WORKSHOP / riscv-myth-workshop-sep23-fayizferosh

Star

5 Day RISC-V pipelined core development using TL-Verilog workshop by VSD

c gcc asm verification gcc-complier verilog risc-v rv32i picorv32 riscv32 riscv-emulator tl-verilog makerchip

Updated Oct 18, 2023
Verilog

fjpolo / edXBuildingARISCVCPUCore

Star

edX LinuxFoundationX LFD111x Building a RISC-V CPU Core

fpga verilog edx risc-v linuxfoundation linuxfoundationx tl-verilog makerchip

Updated Mar 10, 2021

Eyantra698Sumanto / Digital-Design-on-FPGA

Star

This repo contains documentation of the "VSD Open Digital-Design-on-FPGA" tutorial.

fpga vsd verilog systemverilog tl-verilog makerchip virtual-fpga

Updated Jul 17, 2022

amitops2103 / verilog-space-commander

Star

An intelligent, Verilog-based AI fleet controller for the Makerchip ASIC Design Showdown 2025. stellar-strike-ai combines predictive targeting, adaptive defense, and boundary-safe maneuvering to dominate in real-time space combat. Designed using TL-Verilog and fully compatible with the Makerchip simulation environment.

verilog systemverilog showdown makerchip

Updated Sep 1, 2025
TL-Verilog

xevozen / 3bit-PWM-Generator-using-eSim

Star

3bit digitally controlled PWM Generator using eSim, using ngveri(Makerchip) and ngspice

verilog pwm mixed-signal ngspice circuit-design esim pwm-generator makerchip fossee

Updated Jun 18, 2022
Verilog

Ashritv / Building-a-RISC-V-CPU-Core

Star

This Repository Contains my TL-Verilog code Developed During Completion of Course Titled "Building a RISC-V CPU Core" offered by the Linux Foundation through edX

riscv computer-architecture digital-logic-design tl-verilog makerchip

Updated Aug 14, 2024
TL-Verilog

egimelle / singlecycle-cpu

Star

Single-cycle RV32I CPU core

cpu rtl verilog computer-architecture vlsi risc-v open-source-hardware rv32i hardware-design tl-verilog makerchip

Updated Feb 3, 2026
M4

maazm007 / riscv-myth-core

Star

This repository contains the design of RISC-V CPU 5-staged Core

riscv microarchitecture tl-verilog makerchip

Updated Mar 19, 2025
Verilog

VishalRoy08 / RISCV-MYTH-Workshop

Star

Five-day RISC-V workshop journey — from ISA fundamentals and ABI to a hand-built, pipelined RV32I CPU core in TL-Verilog.

vsd riscv verilog pipelining computer-architecture risc-v digital-design rv32i cpu-design nasscom tl-verilog makerchip

Updated Aug 9, 2026
Verilog

PreethamSK163 / Project-2-RISC-V-CPU-Design-using-TL-Verilog

Star

A hands-on implementation of a RISC-V CPU — progressing from ISA fundamentals and GNU toolchain to a fully functional 5-stage pipelined processor with hazard resolution, bypassing, and memory operations, designed using TL-Verilog on the Makerchip platform.

hazard-detection risc-v rv32i cpu-design tl-verilog makerchip pipelined-processor

Updated Apr 2, 2026
TL-Verilog

vijay080604 / RISC_V_MASTERY

Star

My learning path of understanding of RISC_V with the help VSD System Design

riscv computer-architecture cpu-design tl-verilog makerchip

Updated Jun 2, 2026

geekboi777 / RISC-V_CPU_Core

Star

This repository contains the working developer code for a RISC-V_CPU_Core made using TL-Verilog , Makerchip IDE, Sandpiper and Verilator.

verilator sandpiper tl-verilog makerchip

Updated Aug 29, 2023
Verilog

chillakalyan / gsoc-tl-verilog-preparation

Star

Preparation repository for GSoC 2026 (FOSSi Foundation) — Exploring TL-Verilog, Makerchip, and AI-assisted Verilog-to-TLV conversion workflows.

riscv verilog gsoc open-source-hardware tl-verilog makerchip fossi-foundation

Updated Mar 30, 2026

chillakalyan / tlv-virtual-fpga-board

Star

Experimental implementation of Microchip IGLOO Nano FPGA board visualization using TL-Verilog and Makerchip Virtual-FPGA-Lab framework.

fpga gsoc tl-verilog makerchip virtual-fpga-lab

Updated Mar 10, 2026
TL-Verilog

Navigation Menu

makerchip

Here are 19 public repositories matching this topic...

os-fpga / Virtual-FPGA-Lab

ShonTaware / RISC-V_Core_4_Stage

AnoushkaTripathi / NASSCOM-RISC-V-based-MYTH-program

ninja3011 / riscv-cpu-core

ChaminduS / Building-a-RISC-V-CPU-Core

RISCV-MYTH-WORKSHOP / riscv-myth-workshop-sep23-fayizferosh

fjpolo / edXBuildingARISCVCPUCore

Eyantra698Sumanto / Digital-Design-on-FPGA

amitops2103 / verilog-space-commander

xevozen / 3bit-PWM-Generator-using-eSim

Ashritv / Building-a-RISC-V-CPU-Core

egimelle / singlecycle-cpu

maazm007 / riscv-myth-core

VishalRoy08 / RISCV-MYTH-Workshop

PreethamSK163 / Project-2-RISC-V-CPU-Design-using-TL-Verilog

vijay080604 / RISC_V_MASTERY

geekboi777 / RISC-V_CPU_Core

chillakalyan / gsoc-tl-verilog-preparation

chillakalyan / tlv-virtual-fpga-board

Add this topic to your repo