Post-synthesis power optimization via dual-Vth cell assignment and gate re-sizing. Scripting in TCL with custom commands written for Synopsys® PrimeTime® and DC Ultra™.
Typical project for Synopsys DC Compiler
An open-source tool for visualizing and analyzing timing paths extracted from Static Timing Analysis (STA) reports.
Its Prime Time! | It is a game based on your knowledge about prime numbers. Let's see how much you know about prime numbers.
Timing path visualization.
A small stupid program I wrote ages ago to find the prime numbers my military time clock shows.
512-bit multi-channel DMA for shared links with channel-aware admission, hybrid buffering, CDC backends and FPGA/ASIC evidence.
Bit-exact streaming lossless codec for OFDM/radar tensors with AXI-Stream, Multi-Engine scaling, FPGA OOC and ASIC STA evidence.
This project provides a TCL command for PrimeTime, enabling a straightforward implementation of a post-synthesis leakage power minimization procedure. Developed as part of a contest project for the course "Synthesis and Optimization of Digital Circuits" at Politecnico di Torino. This tool is designed to streamline power optimization efforts.
TCL flow for post-synthesis leakage power minimization using multi-threshold cell libraries (LVT, SVT, HVT).
AES-128 hardware Trojan insertion and detection using power analysis (DC, VCS, PrimeTime, PrimePower).
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