pyuvm

10G Low Latency Ethernet

A custom AI chip to be taped out soon!

Examples for using pyuvm

Generic testbench for RISC-V CPUs

Ain Shams University | ADI Graduate Project: An FPGA-implemented DDS & correlator for 5G/6G Integrated Sensing and Communication (ISAC).

Apply dataclasses concept to testbench automation in Python

Replay Ethernet pcaps into Verilator via DPI-C. Cycle-accurate AXI-Stream DUT for IPv4 TCP and Soft-RoCEv2 (BTH, PSN, ICRC).

An 8-bit CPU running on a TangNano 9k FPGA. Written in SystemVerilog and tested with PYUVM.

UCIe-inspired chiplet die-to-die link controller in SystemVerilog: CRC-16 flits, Go-Back-N retry, credit flow control, link training, 3 async clock domains. Verified with pyuvm + fault injection (44/44 pass, 100% coverage) and SymbiYosys formal proofs; synthesized to SKY130.

An open-source, from-scratch AI accelerator: RTL, C++ golden model, and a full pyuvm/cocotb verification environment with 7 intentionally-catalogued bugs.

A small power-control IP verified with open tools. Formal found four unseeded bugs; mutation analysis then showed two of five injected defects passed every property written from the specification.