RTL implementation of a configurable single-stage DWT and IDWT accelerator with AXI4-Stream, AXI4-Lite coefficient reconfiguration, fixed-point Q15 processing, and support for software-controlled multi-level wavelet decomposition on FPGA.
verilog vivado systemverilog dwt wavelet wavelet-transform axi-stream systemverilog-simulation vivado-simulator idwt axi-lite discrete-wavelet-transform qmf systemverilog-test-bench symlets verilog-hd
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Updated
Sep 2, 2026 - Verilog