Skip to content
View zerith59's full-sized avatar

Block or report zerith59

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned Loading

  1. VLSI-ROM-PLA-PAL-Verilog VLSI-ROM-PLA-PAL-Verilog Public

    Verilog HDL design & simulation of ROM, PLA, and PAL at gate-level and pseudo-NMOS transistor-level, verified in EDA Playground

    SystemVerilog

  2. Wazeeh/support-ticketing-system Wazeeh/support-ticketing-system Public

    TypeScript 1