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fix(gic): use correct distributor registers for ESPI enable and routing #656

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Merged
chetan-rathore merged 1 commit into from
Oct 23, 2026
Merged

fix(gic): use correct distributor registers for ESPI enable and routing #656

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6 changes: 4 additions & 2 deletions val/driver/gic/v3/gic_v3_extended.c
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Original file line number Diff line number Diff line change
Expand Up @@ -200,7 +200,7 @@ v3_enable_extended_interrupt_source(uint32_t int_id)
/* Calculate register offset and bit position */
regOffset = (int_id - EXTENDED_SPI_START_INTID) / 32;
regShift = (int_id - EXTENDED_SPI_START_INTID) % 32;
val_mmio_write(val_get_gicd_base() + GICD_ICENABLERE + (4 * regOffset), 1 << regShift);
val_mmio_write(val_get_gicd_base() + GICD_ISENABLERE + (4 * regOffset), 1 << regShift);
} else {
/* Calculate register offset and bit position */
regOffset = (int_id - EXTENDED_PPI_REG_OFFSET) / 32;
Expand Down Expand Up @@ -268,7 +268,9 @@ v3_route_extended_interrupt(uint32_t int_id)
Mpidr = read_mpidr_el1();
cpuTarget = Mpidr & (PE_AFF0 | PE_AFF1 | PE_AFF2 | PE_AFF3);

val_mmio_write64(gicd_base + GICD_IROUTERn + (int_id * 8), cpuTarget);
/* ESPI routing registers start at GICD_IROUTERnE; INTID 4096 maps to register 0 */
val_mmio_write64(gicd_base + GICD_IROUTERnE +
((int_id - EXTENDED_SPI_START_INTID) * 8U), cpuTarget);
}

/**
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1 change: 1 addition & 0 deletions val/include/acs_gic.h
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Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@
#define GICD_IROUTER 0x6000
#define GICD_PIDR2 0xFFE8

#define GICD_ISENABLERE 0x1200
#define GICD_ICENABLERE 0x1400
#define GICD_ICPENDRE0 0x1800
#define GICD_ICACTIVERE0 0x1C00
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