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DR G2L × ISA stream lab: one lane binding feeding a cube fold and an AMX BF16 GEMM - #1983

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AdaWorldAPI merged 3 commits into
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ccr-8062bcc7-l7lkz9-isa-lab
Nov 8, 2026
Merged

AdaWorldAPI merged 3 commits into
mainfrom
ccr-8062bcc7-l7lkz9-isa-lab

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Question

Can one source-witnessed DT64 lane binding feed two different computations, without a second value layout?

  • Cube fold: 16 WHERE masks folded over a 256×256 identity cube.
  • BF16 tile GEMM: AMX TDPBF16PS on this host.

Shape

C[p][m] = Σᵢ lane_p[i] · mask_m(i) gives every SUM(lane p) WHERE mask m in one GEMM:

  • M = 16 demanded lanes
  • N = 16 masks
  • K = the padded population

The cube arm computes the same 16×16 answer by folding positionally. Both arms consume the same LaneBinding, and both must match an oracle built from the fixture alone.

Result

Source data streams directly. The selection needs one bounded staging step.

  • A is read in place. The source's lanes go straight into AMX tiles when they share one allocation, sit at consecutive rows, and have a uniform pitch padded to 32.
  • B is staged once per mask set. B is the WHERE result itself, a 0/1 matrix.
  • No DR or DT64 change. The geometry travels on the source's own LaneSource::Lane type (SlabLane { slab, row, pitch, n }). DR still describes only identity and row order.
  • The one API gap was in ndarray. The safe GEMM entry hardcoded A's row stride to K. Add a strided-A entry to the BF16 tile GEMM ndarray#414 closes it. This PR stays a draft until that merges, because CI checks out ndarray's default branch.

Measured on a Granite Rapids VM (AMX), n = 65,536, 16 lanes × 16 masks. Every timed run is checked against the oracle.

Stage Cost
Bind (cold) 1.0 µs
16 WHERE counts (popcount) 2.2 µs
Stage selection B (cold, 2 MiB) 689 µs
GEMM, A in place 152 µs
GEMM, A staged 362 µs

AMX costs about 43 ns per 16×16×32 block, plus about 105 ns fixed per call. Issuing one call per 32-identity block therefore costs 2.2 ms. A consumer must make one call per row tile with K = the population. The two slow paths are kept in the bench as labelled references, not gates.

Falsifiers

Positive. Both arms are exact against the oracle at n = 256, 513, 4096 and 65,536. Each arm resolves 16 lanes whatever n is. Direct mode copies zero A bytes.

Refusals (each correct path also runs staged):

  • A lane in another row order is refused at bind. If read positionally anyway, the answer is wrong and the oracle catches it.
  • A stale frame refuses both arms; re-binding is accepted again.
  • Masks or a selection from another row order are refused.
  • Scattered lanes, permuted rows, an unpadded pitch, and fewer than 16 lanes each refuse direct mode and stage correctly.
  • bf16 exactness: integers in [-256, 256] are exact, 257 is refused, and decimals report their rounding error.

Disable runs. Removing each of the six lab guards fails exactly the test that names it.

Not done

  • MKL comparison: MKL is not installed here.
  • 32×128 and 64×64 layouts.
  • Certification on dedicated silicon. AMX tile state can corrupt on an oversubscribed VM, which is why every timed result is checked.
  • A faster B staging.

Files


Generated by Claude Code

One DT64 lane binding consumed by two computation geometries over the
same source-owned bf16 lanes: ARM A folds 16 WHERE masks over a 256x256
identity cube, ARM B computes the same 16x16 SUM(lane) WHERE mask answer
as a BF16 tile GEMM (AMX TDPBF16PS on this host), with A read in place
from the slab when 16 demanded lanes are consecutive rows at a padded
pitch, and staged otherwise. B is the selection, staged from the mask
words once per mask set.

Tests: both arms exact against a fixture oracle at n = 256, 513, 4096 and
65536; refusals for a lane in another row order, a stale frame, masks in
another space, scattered lanes, permuted rows, an unpadded pitch and a
partial row tile; bf16 exactness.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01XAqKMMWgnUU9g7Ldyn6sbk
The workflow runs fmt, clippy, the tests and the stage-cost probe on the
runner's own tier and prints which tier ran. The entry records the
contract map, the result matrix, the measured costs and the handoff for
report-rs #33.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01XAqKMMWgnUU9g7Ldyn6sbk
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Codex Review Summary: ✅ Completed

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📝 Code Review ✅ Completed 2026-11-08T00:43:03.061979Z d15115a Draft marked ready
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💡 Codex Review

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Reviewed commit: d15115a9d5

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Comment thread crates/dr-isa-stream-lab/src/fixture.rs Resolved
`i32::MAX as f32` rounds to 2^31, whose low 16 bits are zero, and casting
it back to i32 saturates to i32::MAX, so the check passed a value bf16
cannot hold. f64 holds every i32 and every f32 exactly.

The boundary test covers i32::MAX, i32::MAX - 1 and i32::MIN + 1 (refused)
and i32::MIN, +-2^30 and 3*2^28 (exact, decoded in f64). It failed on
i32::MAX before the fix.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01XAqKMMWgnUU9g7Ldyn6sbk

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excluded-crate fmt, clippy and tests is red because of ndarray, not this PR.

The runner has no AMX, so bf16_tile_gemm_16x16_packed_strided falls to the F32x16 polyfill. On ndarray master that polyfill asserts A must be 16xK BF16 row-major (131072 vs 65536) for any A longer than 16·K, which a strided or row-tile slice always is. The failing test is parity::one_binding_serves_the_cube_fold_and_the_tile_gemm_exactly.

The fix is AdaWorldAPI/ndarray#415. With it, and the fallback forced on an AMX host, all lab tests pass. Once #415 merges I'll re-run this job. The lab code itself needs no change for this. The bf16 exactness fix in b7922b8 is unrelated, for the Codex thread.


Generated by Claude Code

@AdaWorldAPI
AdaWorldAPI merged commit c4ad06d into main Nov 8, 2026
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