[AdaWorldAPI]

ndarray::simd::U16x32 had a different method set on each backend, and there was no way to get from U16x32 to F32x16. Code written against the facade couldn't use zero(), min/max, saturating arithmetic, the compare masks or the u16→f32 widening portably. This gives every backend the same surface and fixes two AVX-512 bugs the new parity test found.

Consumer: turbovec's AVX2 FastScan kernel, rewritten against ndarray::simd at 64-byte width (U8x64 loads → U16x32 accumulators → F32x16 flush). Its flush needs to_f32x16_lo/to_f32x16_hi.

Added (AVX-512, AVX2, AVX-without-AVX2, scalar, nightly):

• zero, simd_min/simd_max, saturating_add/saturating_sub
• cmpeq_mask/cmpgt_mask returning a u32 bitmask (lane i in bit i)
• reduce_min/reduce_max
• to_f32x16_lo/to_f32x16_hi (every u16 is exact in f32)
• AVX-512 only: BitAnd/BitOr/BitXor (+ *Assign), Not, SubAssign, Default, which the other backends already had
• nightly only: from_u8x64_lo/from_u8x64_hi, shl/shr, mullo, pack_saturate_u8, which the other backends already had

How each backend realizes them:

• AVX2: two 256-bit halves, gated off the AVX-without-AVX2 arm. The unsigned > is max(a, b) == a && a != b, so no signed compare is involved. Reductions fold to 128 bits and finish with minpos_epu16.
• AVX-without-AVX2: simd_avx.rs supplies the same methods from four 128-bit SSE quarters.
• Scalar: per-lane loops, which the facade-stride rule allows only in this backend.

Changed:

• U16x32::reduce_sum returns u16 (wrapping) on AVX-512 as well. It returned u32 there and u16 on every other backend. No caller in this repo.

Fixed (both pre-existing on AVX-512):

• shl/shr returned 0 for every count other than 1, 2, 4 and 8, including shl(0). They now use the variable-count sll_epi16/srl_epi16, which also gives 0 for counts ≥ 16, matching the other backends.
• pack_saturate_u8 used packus_epi16, which saturates as signed (a lane ≥ 0x8000 became 0) and interleaves its two inputs per 128-bit lane. It now uses cvtusepi16_epi8 per input, so bytes 0..32 come from self and 32..64 from other, as on the other backends. No caller in this repo.

Parity test: simd::u16x32_facade_parity covers every method against a plain-array reference. The corpus mixes a fixed-seed generator with the edge values 0, 1, 255, 256, 0x7FFF, 0x8000 and 0xFFFF, and checks more than 5000 pairs for the element-wise ops.

arm	how	result
AVX-512	default build (target-cpu=native, AVX-512 host)	4/4
AVX2	--config .cargo/config-v3.toml	4/4
AVX without AVX2	--config .cargo/config-avx.toml, qemu-x86_64-static -cpu SandyBridge	4/4
scalar (also serves NEON and wasm)	--config .cargo/config-v2.toml, qemu-x86_64-static -cpu Nehalem	4/4
nightly-simd	cargo +nightly test --features nightly-simd	4/4

Other gates:

• The full lib suite passes on the default build: 2653 passed, 0 failed.
• The 22 U16x32 doc examples pass.
• cargo fmt --check is clean, and facet-stride-guard.sh --diff origin/master exits 0.
• cargo clippy --lib -- -D warnings is clean on the default, v3 and v2 builds.
• On the AVX arm, clippy fails on master too, and none of its errors is in the new code.
• Disable run: making the AVX2 cmpgt_mask compute >= turns the AVX2 parity run red.

Not done: no bench against scalar yet (acceptance criterion 4). The consumer PR in turbovec measures the kernel end to end.

---

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