Project period: August 2025 – December 2025
This project connects transistor-level cell design with an RTL-to-layout flow in GF 65 nm CMOS. It follows the development of a custom cell library, its characterization, and its use in a 32-bit arithmetic logic unit.
- Build and simulate the RTL. Start with a behavioral 16-bit ALU and testbench in Vivado, then develop a synthesizable 32-bit implementation.
- Develop the basic cells. Create CMOS schematics and layouts, beginning with an inverter, and check the designs using DRC, LVS, and parasitic extraction.
- Expand the library. Implement INV, NAND2, NOR2, NAND3, NOR3, AOI332, OAI4331, and a custom 11-input logic function. Add a falling-edge-triggered D flip-flop and characterize its sequential timing.
- Characterize and map. Generate library timing data with PrimeLib, compile the library with Library Compiler, and synthesize the ALU using Design Vision.
- Implement the physical design. Place and route the mapped design in Innovus, inspect the layout in Virtuoso, and evaluate timing using PrimeTime.
| Parameter | Documented value |
|---|---|
| Inverter channel length | 65 nm |
| Inverter PMOS / NMOS widths | 1.9 / 1.5 µm |
| Combinational cell height | 3.312 µm |
| Pin pitch | 0.368 µm |
| Input transition used for characterization | 30 ps |
| Output load used for characterization | 55 fF |
| D flip-flop height | 4.048 µm |
The layout work explores diffusion sharing through Euler paths, metal-layer usage, pin access, and filler-cell geometry. Sequential-cell characterization includes setup time, hold time, and clock-to-Q delay.
The original project documentation records 4,164 cells for the earlier synthesis stage and 7,402 cells for the later custom-library ALU implementation. These are results from different stages, rather than a controlled comparison of library efficiency.
The physical-design notes report a reduction from approximately 2,000 DRC violations to 572 after layout changes. This documents progress in resolving violations; it does not establish a DRC-clean final ALU layout.
| Location | Contents |
|---|---|
| Layout and Schematic | Cell schematic and layout material |
| Verilog Code | HDL project material |
| Synthesis and Netlist | Synthesis and mapped-netlist material |
| Place and Route | Physical implementation material |
The documented flow uses Cadence Virtuoso and Innovus, Synopsys HSPICE, Design Vision, PrimeLib, Library Compiler, and PrimeTime, with Vivado used for the initial behavioral design.
Reproducing the implementation requires compatible EDA tools and access to the relevant process design kit. Reported results describe the original project runs; they have not been regenerated for this portfolio edition.