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  1. YAPP-Router-UVM-Verification YAPP-Router-UVM-Verification Public

    SystemVerilog/UVM verification of a three-channel YAPP packet router: reusable agents, constrained-random traffic, HBUS sequences, and queue-based scoreboarding.

    SystemVerilog

  2. UART-UVM-Verification UART-UVM-Verification Public

    SystemVerilog/UVM UART loopback verification with constrained-random sequences, a transaction scoreboard, and functional coverage.

    SystemVerilog 1

  3. 65nmCMOS-StandardCellLibraryDesign 65nmCMOS-StandardCellLibraryDesign Public

    Custom standard-cell design, characterization, and 32-bit ALU implementation in GF 65 nm CMOS.

    Verilog

  4. 7nmFinFET-StandardCellLibraryDesign 7nmFinFET-StandardCellLibraryDesign Public

    7 nm FinFET standard-cell library, registered 3-bit arithmetic unit, synthesis artifacts, and physical-design reports.

    Verilog

  5. MSDAP-ASAP7-ASIC MSDAP-ASAP7-ASIC Public

    Mini Stereo Digital Audio Processor | ASAP7 7nm ASIC design | Stereo Verilog RTL, SRAM integration, Genus synthesis, Innovus physical implementation, and verification documentation.

    Verilog