Hadlee Julietraj · The University of Texas at Dallas · EEDG/CE 6306 ASIC Design · January–May 2026
Team project with Dhanyashree Reddy.
A stereo digital audio processor implemented through an ASIC design flow: serial audio interfaces, convolution datapaths, control FSMs, SRAM integration, synthesis, and physical implementation using the ASAP7 7 nm predictive PDK.
The design processes left and right audio streams independently while sharing control. Its convolution engine uses signed accumulation and one-bit shifts to reduce arithmetic hardware complexity. This repository presents the submitted implementation, supporting reports, and a guided explanation of the engineering decisions.
Start with: architecture · code tour · tools and results · simulation guide
| Aspect | Implementation |
|---|---|
| Audio paths | Left and right serial inputs; independent datapaths and memories |
| Input / result width | 16-bit input samples; 40-bit internal result and serial output in the final RTL |
| Arithmetic | Sign extension, add/subtract accumulation, one-bit arithmetic shifts |
| Memories | Rj table, coefficient descriptors, and circular sample history per channel |
| SRAM integration | 14 macro instances: 8 coefficient, 2 Rj, 4 sample-buffer macros |
| Control | Initialization, table loading, input loading, computation, clearing, sleep/wake |
| Clock target | SCLK 26.88 MHz; DCLK 768 kHz; 35:1 ratio |
| Technology | ASAP7 predictive 7 nm PDK and SRAM macros |
| Implementation artifacts | Verilog, SystemVerilog, Tcl, SDC, CPF, netlists, DEF, SDF, SPEF, timing/area/power reports |
The clock frequencies above are the project target described in the project materials. The archived testbench and constraints use different values. Snapshot status explains this distinction and the outstanding signoff evidence.
flowchart LR
L[Left serial input] --> SL[S2P left]
R[Right serial input] --> SR[S2P right]
SL --> ML[Left Rj / coefficient / sample SRAM]
SR --> MR[Right Rj / coefficient / sample SRAM]
ML --> AL[Left ALU: add, subtract, shift]
MR --> AR[Right ALU: add, subtract, shift]
AL --> PL[P2S left] --> OL[Left serial output]
AR --> PR[P2S right] --> OR[Right serial output]
C[Shared FSM and clock/reset synchronizers] -. enables and addresses .-> ML
C -. enables and addresses .-> MR
C -. compute control .-> AL
C -. compute control .-> AR
- Partitioned the system into datapath, control, serial interfaces, and separate SRAM subsystems for both channels.
- Developed and integrated synthesizable Verilog and module/top-level testbenches, with ModelSim simulation and SpyGlass lint analysis.
- Addressed clock and reset crossings using synchronization logic; the reported project flow also included SpyGlass CDC/RDC analysis.
- Synthesized with Cadence Genus and integrated ASAP7 SRAM macros. Generated formal-verification setup is present; Cadence Conformal LEC is part of the reported flow.
- Performed floorplanning, placement, clock-tree work, routing, and extraction in Cadence Innovus.
- The reported full project flow included Synopsys PrimeTime STA and Siemens Calibre DRC/LVS. Passing final signoff reports are pending addition; the saved April implementation reports contain violations.
These are team-project activities. Course-supplied code and existing author credits are retained; see attribution.
implementation/
Verilog_Soln_HW6/ Final stereo RTL and SystemVerilog testbench
Memory/verilog/ SRAM integration wrappers and simulation models
syn/ Genus script, constraints, netlist, synthesis reports
Innovus/ Floorplan, power, MMMC, routing scripts and implementation outputs
compile.tcl Original ModelSim flow
data*.in / data*.out Submitted stimulus and saved outputs
history/midterm/ Earlier RTL and module testbenches
reports/ Compact saved simulation evidence
docs/ Architecture, walkthrough, tools, reproducibility
scripts/ Isolated simulation runner
SOURCE_MANIFEST.csv Source provenance and published-file hashes
The archived simulation transcript ends with 0 errors and 0 warnings. The HW07 report states that gate-level output matched behavioral output. A completed simulation is not by itself an independent golden-vector comparison.
The saved Innovus setup summary reports WNS −342.635 in its report units, so this snapshot does not establish timing closure. The owner has confirmed that a later signoff package exists; those reports are not yet included. Final signoff evidence will be documented when the later package is available.
Commercial EDA tools and the external PDK are required to reproduce the complete physical flow. The repository includes useful design artifacts, while large proprietary tool databases and PDK library payloads remain outside Git. See running the design.