asap7

Here are 9 public repositories matching this topic...

Kev1nLevin / matmul-engine

Parameterized N×N output-stationary systolic array accelerator for INT8 neural network inference. Full RTL-to-GDS flow on ASAP7 7nm using Cadence Genus + Innovus. 667 MHz, 42.7 GOPS peak throughput, 0.33 mW/GOP. SystemVerilog RTL, synthesis, place-and-route and self-checking testbench included.

neural-network accelerator systemverilog vlsi cadence digital-design genus tpu physical-design innovus 7nm rtl-to-gds systolic-array asap7

Updated Feb 18, 2026
Verilog

tanfer-meta / vercore

Star

Autonomous RISC-V CPU replication of 'Design Conductor' (arxiv:2603.08716) — 1.525 GHz, 2,358 µm² cell area, CoreMark 9,541, ASAP7 SLVT, open-source EDA only. Personal side project.

asic cpu eda verilog risc-v autonomous-agents coremark gdsii openroad asap7

Updated May 4, 2026
Verilog

Lord1Egypt / KemetCore

Star

Open-source silicon: 10 hardware accelerator projects from SystemVerilog RTL to 7nm GDSII. CPUs (RISC-V + RVV), ML accelerators (conv, attention, sparse matmul, FP8/BF16), crypto (SHA-256/3, ML-KEM), graphics (ray-trace), and FPU library — all with bit-exact pymodel verification and cocotb tests.

Updated Aug 17, 2026
Python

DfX-NYUAD / Trojan-Insertion-versus-Layout-Defenses

Star

Benchmarking framework for ISPD'23 contest and TCHES'25 paper.

contest eco hardware-security trojans ispd physical-design security-closure hardware-trojans red-vs-blue asap7 tches

Updated Sep 26, 2025
Shell

Lord1Egypt / PtahCore

Star

𓁰 PtahCore — open-source FP8 tensor accelerator, RTL→GDSII on open 7nm ASAP7, 100% open toolchain

Updated Jul 2, 2026
Tcl

Puji7tha / finfet-domino-sram-asap7

Star

Transistor-level design and characterization in ASAP7 7nm FinFET: a dual-Vt domino AND8 (11% leakage reduction) and 6T vs 8T SRAM bitcells across read, write, and hold. Includes a measurement-setup discrepancy found in the original decks.

sram vlsi cadence-virtuoso finfet hspice circuit-design 7nm low-power-design asap7 domino-logic

Updated Sep 8, 2026
SourcePawn

Hadleeraj / MSDAP-ASAP7-ASIC

Star

Mini Stereo Digital Audio Processor | ASAP7 7nm ASIC design | Stereo Verilog RTL, SRAM integration, Genus synthesis, Innovus physical implementation, and verification documentation.

asic verilog sram systemverilog digital-signal-processing vlsi cadence-innovus asap7 rtl-to-gdsii

Updated Sep 11, 2026
Verilog

bojieli / OpenTallas

Star

Open research toward model-specific mask-ROM LLM inference silicon: analytical studies, an ABI 3.0 compiler/runtime and cycle model, synthesizable RTL, and open-PDK physical evidence — gated against itself by a 19-rung board that is deliberately mostly red.