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The initial blocks of a Veryl `#[test]` module are compiled into process kernels and run by the timed scheduler instead of the testbench bytecode interpreter, which stays as a fallback behind `SimulatorBuilder::testbench_kernels(false)`. The frontend lowers each block with the procedural expression lowering over the elaborated instance's stable state. Loop counters and bounds live in state so a wait inside a loop can suspend; each block owns a copy of the function-local variables; a hierarchical reference is a synthetic variable addressing the child's state. Clock waits become clock waits with fused ticks, `rst.assert` a clock wait with a release, random numbers and component methods host requests served through scratch state, and a read of design state after a store settles the combinational logic first through the new `Settle` status. The scheduler applies releases as events of their domain, fires the falling and rising edges of a time together after the processes ran, treats an edge from an unknown four-state value as an edge, and stops resuming processes once the tick budget is spent. Hash maps embedded in native images serialize in key order so a build cache round trip reproduces the image. BREAKING CHANGE: `%t` in a testbench and the time a component's finish hook observes are the scheduler time, in which the default process clock has period 2; single-process testbenches previously saw the tick count.
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Merging this PR will not alter performance
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- Track the dirty state per branch side and merge it at the join, so a read after a branch whose one side stored and whose other side waited settles the logic. - Settle the logic a component's output writes feed before the kernel resumes. - Plan scratch state like the lowering: a side a constant condition keeps out, and a loop over a constant-empty range, take none. - Resume a process at once after its host request is served, as the `Host` status documents; no other process runs inside the statement. - A `$finish` of the design's own logic completes the kernel run and is not reported as a tick limit. - Four-state edge detection follows IEEE 1800-2023 Table 9-2 in both edge paths: changes into x or z from 0 or 1 are edges too. - Validate the index and select geometry of a hierarchical destination like a local one.
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# Conflicts: # crates/celox-runtime/src/simulation.rs # crates/celox/tests/processes.rs
- A kernel yields to the host every 256 runtime events, and the executor takes the events out of the ring at each yield, so an uninterrupted block with many `$assert`s or `$display`s loses none. - A block that ends right after a store settles first. - `clk.next(0)` continues at once; a reset release settles before the released process reads. - The runner starts every process clock low, reads a component's completion request before the teardown, tears the components down when the initial settling fails, and runs as kernels only when the schema marks a Veryl testbench (`RuntimeSchema::testbench_kernels`), which also keeps a design's own processes among the RTL writers.
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# Conflicts: # crates/celox/src/simulator.rs
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# Conflicts: # crates/celox-runtime/src/simulation.rs
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…/1123-clock-waits # Conflicts: # crates/celox-runtime/src/simulation.rs
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# Conflicts: # crates/celox-runtime/src/simulation.rs # crates/celox/src/simulation.rs
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# Conflicts: # crates/celox-design/src/lib.rs # crates/celox-frontend-core/src/process.rs # crates/celox-runtime/src/simulation.rs # crates/celox/src/backend/native/image_file.rs # crates/celox/src/simulation.rs
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Converted to draft: superseded by the redesign in #1123 (comment). Kept as a reference implementation; it will be closed when its replacement merges. |
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Stacked on #1160, part of #1123. Veryl test initial blocks compile to timed process kernels; testbench_kernels(false) retains the bytecode runner. Kernels preserve helper order, short-circuit/four-state behavior, copy-back, suspended storage, clock/reset waits and assertion output. Terminating expression arms contribute no continuation or dirtiness to a join, while writing arms that return still settle before reads.
Pending display/write bytes are forwarded before later component/file host requests, retaining assertion and finish events for normal draining. Completed clock-release settles are reused by clean continuations. Generated clocks reset and derived inputs settle before component initialization; an interrupted reset restores release targets before the next run while preserving first-run reset counts. Existing component expectations remain unchanged.
Internal/component/release settles capture transient FF occurrences before continuations can erase them. Ordinary Finish stops immediately; Veryl FinishAfterPublication preserves the final publication boundary. The inherited SV loop budget resumes the same process immediately, and interrupted/zero-count continuations retain runnable work. Rust host writes share readiness/edge publication across modify and direct setters, including eager runtime-event drain settling and intervening reads/evaluation. Host readiness uses a checkpointed explicit marker, and all backends retain Finish independently of diagnostic-ring overflow.
Native container32 validates counters, offsets, testbench boundaries, clocks, releases, host requests, tick-loop eligibility and the new Finish header ABI. Attachment requires a trusted whole artifact, including code and ABI metadata. Host paths retain declared bytes/strict UTF-8, outgoing values are snapshotted before reentrant selectors, and suspended values retain X/Z. Ordered preprocessing, typed external drivers and cross-file package initializer probes are integrated from #1159; zero-trip dependency proofs retain executed headers while excluding unreachable bodies/steps.
Validation: library288, SV3156 (20 existing exclusions), checkpoint30, component63, SDK13, concurrent initial/runtime99 and stepping7 pass. NAPI is freshly rebuilt; all437 JavaScript tests plus types/lint pass. Formatting and affected all-target clippy pass. Public API regressions reproduce the pre-fix readiness failures and check actual execution across four backends; portable zero-trip and cross-file initializer cases are wired into the shared harness. The128-case independent timing comparison passes124 Icarus and126 Verilator cases with only existing exclusions/limitations, and all10 live adapter integrations pass. Imported CI/queue configuration passes47 script tests; this import changes no product/test/dependency inputs, so successful product validation is reused. Retained reports/exclusions were not refreshed. Full platform and latest-head CI remain required before merge.