New LogicArrayOf datatype

.devcontainer/devcontainer.json

@@ -4,6 +4,12 @@
 {
   "image": "mcr.microsoft.com/devcontainers/base:ubuntu-24.04",
 
+  "features": {
+    "ghcr.io/devcontainers/features/node:1": {
+      "version": "24"
+    }
+  },
+
   "updateContentCommand": "tool/gh_codespaces/run_setup.sh",
 
   "customizations": {

.github/configs/mlc_config.json

@@ -27,11 +27,20 @@
     {
       "pattern": "^https://code\\.visualstudio\\.com/"
     },
+    {
+      "pattern": "^https://marketplace\\.visualstudio\\.com/items\\?itemName=Dart-Code\\.dart-code$"
+    },
+    {
+      "pattern": "^https://raw\\.githubusercontent\\.com/intel/rohd/refs/heads/badges/coverage/rohd_devtools_extension/main\\.svg$"
+    },
     {
       "pattern": "^https://www.nandland.com"
     },
     {
       "pattern":"^https://.*\\.fandom\\.com"
+    },
+    {
+      "pattern": "^https://intel\\.github\\.io/rohd/rohd/"
     }
   ]
 }

.github/workflows/coverage.yml

@@ -37,6 +37,22 @@ jobs:
       - name: Generate coverage and badge
         run: tool/generate_coverage.sh --generate-svg
 
+      - name: Save ROHD coverage badge
+        run: cp /tmp/coverage-badge.svg /tmp/rohd-coverage-badge.svg
+
+      - name: Setup Flutter
+        uses: flutter-actions/setup-flutter@v2
+        with:
+          channel: stable
+          version: 3.47.2
+
+      - name: Install DevTools dependencies
+        run: flutter pub get --directory=rohd_devtools_extension
+
+      - name: Generate DevTools coverage and badge
+        working-directory: rohd_devtools_extension
+        run: ../tool/generate_coverage.sh --generate-svg
+
       - name: Commit coverage badge
         run: |
           BRANCH_NAME="${{ github.ref_name }}"
@@ -49,10 +65,11 @@ jobs:
 
           # Clean and copy badge
           git rm -rf . 2>/dev/null || true
-          mkdir -p coverage
-          cp /tmp/coverage-badge.svg "coverage/${BRANCH_NAME}.svg"
+          mkdir -p coverage/rohd_devtools_extension
+          cp /tmp/rohd-coverage-badge.svg "coverage/${BRANCH_NAME}.svg"
+          cp /tmp/coverage-badge.svg "coverage/rohd_devtools_extension/${BRANCH_NAME}.svg"
 
-          git add "coverage/${BRANCH_NAME}.svg"
+          git add "coverage/${BRANCH_NAME}.svg" "coverage/rohd_devtools_extension/${BRANCH_NAME}.svg"
           git diff --staged --quiet || git commit -m "Update coverage badge for ${BRANCH_NAME} [skip ci]"
 
           git push origin badges --force

.github/workflows/general.yml

@@ -114,10 +114,6 @@ jobs:
         if: matrix.platform == 'vm'
         run: bash tool/gh_actions/install_gtkwave.sh
 
-      - name: Install software - GTKWave
-        if: matrix.platform == 'vm'
-        run: bash tool/gh_actions/install_gtkwave.sh
-
       - name: Run project tests
         run: tool/gh_actions/run_tests.sh ${{ matrix.platform }}
 

CHANGELOG.md

@@ -15,6 +15,7 @@
 
 ### Major Features
 
+- Added `TypedLogicArray<TLogic, TValue>` for multidimensional arrays with fixed typed hardware elements and associated semantic values, including typed snapshots and ports, traversal, cloning, net support, and synthesis. Added shaped `LogicValueArray` and codec-backed `TypedLogicValueArray<TValue>` values with nested construction, packed `LogicValue` interoperability, and hardware-array assignment. Existing `LogicArray`, `LogicValueArray`, and concrete array port APIs remain available as specializations (<https://github.com/intel/rohd/pull/686>).
 - Added `LogicEnum<T>` hardware signals with explicit enum encodings, mapped member assignments, driveable cloning, and SystemVerilog enum generation (<https://github.com/intel/rohd/pull/599>).
 - Added compact FST waveform capture alongside VCD, with block-based reading and waveform query APIs for incremental access (<https://github.com/intel/rohd/pull/671>).
 - Added SystemC generation, runtime support, and `SystemCService` for generating and writing module artifacts. Generated SystemC uses a two-state representation and does not preserve X/Z semantics (<https://github.com/intel/rohd/pull/662>).
@@ -27,14 +28,20 @@
 
 ### Improvements
 
+- Improved generated synthesis wiring across module boundaries and driver-name selection (<https://github.com/intel/rohd/pull/726>).
+- Same-width `Logic.zeroExtend` now returns the original signal instead of creating a redundant extension (<https://github.com/intel/rohd/pull/729>).
+- Migrated `rohd_source_navigator` into its package in preparation for independent publication (<https://github.com/intel/rohd/pull/718>).
 - Netlist JSON format is now `0.1.0`, preserving enum types and encodings on retained netnames using Yosys-style attributes, including constant-driven enum uses (<https://github.com/intel/rohd/pull/599>).
+- Refined the typed-array hierarchy so `LogicArray` directly specializes `TypedLogicArray<Logic, LogicValue>`, and strengthened custom `TypedLogicArray` cloning to preserve runtime types, codecs, unpacked dimensions, and constructor-only naming prefixes without exposing them as public axis metadata (<https://github.com/intel/rohd/pull/686>).
+- Expanded `TypedLogicArray` support for recursively nested typed and ordinary arrays, structures containing array fields, mixed packed/unpacked dimensions, structured net and inout ports, and recursive netlist type metadata. Fixed generated SystemVerilog for array-valued elements to use packed offsets consistent with declarations and module-port connections, avoiding invalid chained selections in Icarus and Verilator (<https://github.com/intel/rohd/pull/686>).
 - Added configurable waveform timescales, recording windows, and output overwrite policies (<https://github.com/intel/rohd/pull/671>).
 - Added opt-in `DebugSession` setup for source tracing, netlist and FLC services, and live waveform recording (<https://github.com/intel/rohd/pull/707>).
 - Expanded reusable `rohd_devtools_widgets` components for hierarchy browsing, signal formatting, bit expansion, overlays, help, capture, and cross-probing (<https://github.com/intel/rohd/pull/736>).
 - Added `rohd_waveform` 0.1.1 client APIs for hierarchy normalization, repository-backed waveform access, caching, readiness, streaming, computed signals, and sub-field/bit-slice waveforms (<https://github.com/intel/rohd/pull/736>).
 
 ### Bug Fixes
 
+- Fixed a netlist pass that could drop connections to module output ports (<https://github.com/intel/rohd/pull/731>).
 - Fixed `LogicValue.ofRadixString` round trips with empty separators and separators containing regular-expression metacharacters (<https://github.com/intel/rohd/issues/722>).
 
 ## 0.6.11

README.md

@@ -38,28 +38,32 @@ You can also open this repository in a GitHub Codespace to run the example in yo
 ## About ROHD
 
 - Full power of the modern **Dart language** for hardware design and verification
-- Makes **validation collateral** simpler to develop and debug.  The [ROHD Verification Framework](https://github.com/intel/rohd-vf) helps build well-structured testbenches.
+- Can use the excellent pub.dev **package manager** and all the packages it has to offer
 - Develop **layers of abstraction** within a hardware design, making it more flexible and powerful
-- Easy **IP integration** and **interfaces**; using an IP is as easy as an import.  Reduces tedious, redundant, and error prone aspects of integration
+- **Less verbose** than alternatives (fewer lines of code)
+- Fewer bugs and lines of code means **shorter development schedule**
+- Enables **higher quality** development
 - **Simple and fast build**, free of complex build systems and EDA vendor tools
-- Can use the excellent pub.dev **package manager** and all the packages it has to offer
-- Built-in event-based **fast simulator** with **4-value** (0, 1, X, and Z) support and a **waveform capture service** to .vcd or .fst file format
+- Excellent, simple, fast **unit-testing** framework
+- Simulate with **various abstraction levels of models** from architectural, to functional, to cycle-accurate, to RTL levels in the same language and environment
+- Simple, free, **open source tool stack** without any headaches from library dependencies, file ordering, elaboration/analysis options, +defines, etc.
+- Use **modern IDEs** like Visual Studio Code, with excellent static analysis, fast autocomplete, built-in debugger, linting, git integration, extensions, and much more
+- Easy **IP integration** and **interfaces**; using an IP is as easy as an import.  Reduces tedious, redundant, and error prone aspects of integration
 - Conversion of modules to human-readable, structurally similar **SystemVerilog** and **SystemC** for integration or downstream tool consumption
 - **Run-time dynamic** module port definitions (numbers, names, widths, etc.) and internal module logic, including recursive module contents
-- Leverage the [ROHD Hardware Component Library (ROHD-HCL)](https://github.com/intel/rohd-hcl) with reusable and configurable design and verification components.
-- Simple, free, **open source tool stack** without any headaches from library dependencies, file ordering, elaboration/analysis options, +defines, etc.
-- Excellent, simple, fast **unit-testing** framework
-- **Less verbose** than alternatives (fewer lines of code)
-- Enables **higher quality** development
 - Replaces hacky perl/python scripting for automation with powerful **native control of design generation**
-- Fewer bugs and lines of code means **shorter development schedule**
-- Support for **cosimulation with verilog modules** (via [ROHD Cosim](https://github.com/intel/rohd-cosim)) and **instantiation of verilog modules** in generated SystemVerilog code
-- Use **modern IDEs** like Visual Studio Code, with excellent static analysis, fast autocomplete, built-in debugger, linting, git integration, extensions, and much more
-- Simulate with **various abstraction levels of models** from architectural, to functional, to cycle-accurate, to RTL levels in the same language and environment.
 
-ROHD is *not* a new language, it is *not* a hardware description language (HDL), and it is *not* a version of High-Level Synthesis (HLS).  ROHD can be classified as a generator framework.
+- The **ROHD Framework** is a complete design and verification framework:
+  - Built-in event-based **fast simulator** with **4-value** (0, 1, X, and Z) support and a **waveform capture service** to .vcd or .fst file format
+  - Leverage the [ROHD Hardware Component Library (ROHD-HCL)](https://github.com/intel/rohd-hcl) with reusable and configurable design and verification components
+  - Makes **validation collateral** simpler to develop and debug.  The [ROHD Verification Framework](https://github.com/intel/rohd-vf) helps build well-structured testbenches
+  - Powerful capabilities like the [ROHD Schematic Viewer](https://github.com/rohd-schematic-viewer) for high-fidelity rendering of ROHD designs as well as [ROHD Wave Viewer](https://github.com/rohd-wave-viewer) for viewing simulation waveforms even for complex ROHD structures
+  - Debug your design with [ROHD Live Debugger](https://github.com/intel/rohd/rohd_devtools_extension), an integrated debugger with cross-probing into ROHD source and synthesized RTL output from schematics rendering and waveform display all connected to live RTL simulation
+  - Support for **cosimulation with verilog modules** (via [ROHD Cosim](https://github.com/intel/rohd-cosim)) and **instantiation of verilog modules** in generated SystemVerilog code
+
+ROHD is *not* a new language, it is *not* a hardware description language (HDL), and it is *not* a version of High-Level Synthesis (HLS).  ROHD can be classified as a generator framework, extending a powerful software language into the hardware domain and providing a full suite of tools and capabilities to accelerate hardware design and validation.
 
-You can think of this project as an attempt to *replace* SystemVerilog and related build systems as the front-end methodology of choice in the industry.
+You can think of this project as an attempt to *replace* SystemVerilog and related design systems as the front-end methodology of choice in the industry.
 
 One of ROHD's goals is to help grow an open-source community around reusable hardware designs and verification components.
 

doc/releases.md

@@ -167,10 +167,13 @@ It runs `pub get` and `pub downgrade`, each followed by fatal-info analysis of
 downgraded resolution. Required dependencies must already be available on pub.dev;
 there is no fallback to local packages. Command failures stop CI and preparation.
 Pana's report is printed for review, and package scoring findings such as missing
-examples or newer dependency major versions block CI and preparation, matching
-the root package's policy. The runner passes `--exit-code-threshold 0` for every
-sub-package, requiring a full score. The sole temporary exception is
-`rohd_source_navigator`, which uses threshold `10` while its canonical
+examples or newer dependency major versions count against the CI and preparation
+score gate. Pana's `--exit-code-threshold` is the number of
+points that may be lost from its 160-point maximum: `0` requires a full score.
+`rohd_devtools_widgets` permits up to 10 points lost (a minimum score of 150)
+while newer `cupertino_ui` and `material_ui` releases require a Dart SDK
+upgrade and accompanying formatter changes. `rohd_source_navigator` also uses
+threshold `10` temporarily while its canonical
 `https://github.com/intel/rohd/tree/main/packages/rohd_source_navigator`
 repository URL cannot be validated before the path exists on upstream `main`;
 remove the exception when [#718](https://github.com/intel/rohd/pull/718) merges.