Skip to content

More register definitions - #79

Open
CUB3D wants to merge 8 commits into
rust-embedded:mainfrom
CUB3D:missing_regs2
Open

CUB3D wants to merge 8 commits into
rust-embedded:mainfrom
CUB3D:missing_regs2

Conversation

@CUB3D

@CUB3D CUB3D commented Apr 2, 2026 •

Copy link
Copy Markdown
Contributor

Adds:

  • accdata_el1
  • actlrmask_el1
  • actlrmask_el2
  • afsr0_el2
  • afsr0_el3
  • ccsidr2_el1
  • hacr_el2
  • id_aa64isar2_el1
  • id_aa64isar3_el1
  • osdlr_el1
  • tpidr_e3

Expands field definitions for:

  • id_aa64dfr0_el1
  • id_aa64dfr1_el1
  • id_aa64pfr1_el1

Update (08/10/2026): Marked ready for review after #74 merged

@CUB3D
CUB3D marked this pull request as ready for review October 8, 2026 17:43
@berkus
berkus requested a balanced review from Copilot October 8, 2026 20:17

Copilot AI left a comment

Copy link
Copy Markdown
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

🟡 Changes recommended

Several bitfield register marker types are incorrect, preventing typed field access, alongside an incorrect ACCDATA field width.

15 open findings
What changed in this PR

Adds and exports additional AArch64 system-register definitions while expanding feature-register bitfields.

Changes:

  • Adds register accessors across EL1–EL3.
  • Defines additional architectural feature fields and encodings.
  • Exports the new registers through the public registry.
File Description
registers/​tpidr_el3.rs Adds TPIDR_EL3 access.
registers/​osdlr_el1.rs Adds OS double-lock access.
registers/​id_aa64pfr1_el1.rs Expands processor feature fields.
registers/​id_aa64isar3_el1.rs Adds ISAR3 feature definitions.
registers/​id_aa64isar2_el1.rs Adds ISAR2 feature definitions.
registers/​id_aa64dfr1_el1.rs Expands debug feature definitions.
registers/​id_aa64dfr0_el1.rs Adds DFR0 fields.
registers/​hacr_el2.rs Adds HACR_EL2 access.
registers/​ccsidr2_el1.rs Adds CCSIDR2_EL1 access.
registers/​afsr0_el3.rs Adds EL3 fault-status access.
registers/​afsr0_el2.rs Adds EL2 fault-status access.
registers/​actlrmask_el2.rs Adds EL2 control masking.
registers/​actlrmask_el1.rs Adds EL1 control masking.
registers/​accdata_el1.rs Adds accelerator-data access.
registers.rs Exports the new registers.

🧠 Review effort: Balanced


💡 Add a code-review agent skill or configure MCP servers for context-aware, tailored reviews. Learn more in the docs.

Comment thread packages/aarch64-cpu/src/registers/accdata_el1.rs
Comment thread packages/aarch64-cpu/src/registers/ccsidr2_el1.rs Outdated
Comment thread packages/aarch64-cpu/src/registers/id_aa64dfr1_el1.rs Outdated
Comment thread packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs Outdated
Comment thread packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs Outdated
Comment thread packages/aarch64-cpu/src/registers/id_aa64isar2_el1.rs Outdated
Comment thread packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs Outdated
Comment thread packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs Outdated
Comment thread packages/aarch64-cpu/src/registers/id_aa64isar3_el1.rs Outdated
Comment thread packages/aarch64-cpu/src/registers/id_aa64pfr1_el1.rs Outdated
@berkus

berkus commented Oct 8, 2026

Copy link
Copy Markdown
Member

This is gonna take a while to review, if you could split it into several smaller PRs it could be easier, but if not - don't worry I'll crawl through this one eventually.

@CUB3D

CUB3D commented Oct 9, 2026

Copy link
Copy Markdown
Contributor Author

I'm in no rush and I'd rather not have to wrangle multiple different PRs. But I'll keep it in mind to keep future PRs more focused

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

3 participants