More register definitions

packages/aarch64-cpu/src/registers.rs

@@ -5,10 +5,15 @@
 #[macro_use]
 mod macros;
 
+mod accdata_el1;
 mod actlr_el1;
 mod actlr_el2;
 mod actlr_el3;
+mod actlrmask_el1;
+mod actlrmask_el2;
 mod afsr0_el1;
+mod afsr0_el2;
+mod afsr0_el3;
 mod afsr1_el1;
 mod aidr_el1;
 mod amair_el1;
@@ -22,6 +27,7 @@ mod apiakeyhi_el1;
 mod apiakeylo_el1;
 mod apibkeyhi_el1;
 mod apibkeylo_el1;
+mod ccsidr2_el1;
 mod ccsidr_el1;
 mod clidr_el1;
 mod cntfrq_el0;
@@ -62,6 +68,7 @@ mod far_el1;
 mod far_el2;
 mod far_el3;
 mod fp;
+mod hacr_el2;
 mod hafgrtr_el2;
 mod hcr_el2;
 mod hdfgrtr_el2;
@@ -106,6 +113,8 @@ mod id_aa64dfr0_el1;
 mod id_aa64dfr1_el1;
 mod id_aa64isar0_el1;
 mod id_aa64isar1_el1;
+mod id_aa64isar2_el1;
+mod id_aa64isar3_el1;
 mod id_aa64mmfr0_el1;
 mod id_aa64mmfr1_el1;
 mod id_aa64mmfr2_el1;
@@ -128,6 +137,7 @@ mod mpuir_el2;
 mod mvfr0_el1;
 mod mvfr1_el1;
 mod mvfr2_el1;
+mod osdlr_el1;
 mod oslar_el1;
 mod par_el1;
 mod pmuserenr_el0;
@@ -164,6 +174,7 @@ mod tcr_el2;
 mod tpidr_el0;
 mod tpidr_el1;
 mod tpidr_el2;
+mod tpidr_el3;
 mod tpidrro_el0;
 mod ttbr0_el1;
 mod ttbr0_el2;
@@ -175,10 +186,15 @@ mod vmpidr_el2;
 mod vtcr_el2;
 mod vttbr_el2;
 
+pub use accdata_el1::ACCDATA_EL1;
 pub use actlr_el1::ACTLR_EL1;
 pub use actlr_el2::ACTLR_EL2;
 pub use actlr_el3::ACTLR_EL3;
+pub use actlrmask_el1::ACTLRMASK_EL1;
+pub use actlrmask_el2::ACTLRMASK_EL2;
 pub use afsr0_el1::AFSR0_EL1;
+pub use afsr0_el2::AFSR0_EL2;
+pub use afsr0_el3::AFSR0_EL3;
 pub use afsr1_el1::AFSR1_EL1;
 pub use aidr_el1::AIDR_EL1;
 pub use amair_el1::AMAIR_EL1;
@@ -192,6 +208,7 @@ pub use apiakeyhi_el1::APIAKEYHI_EL1;
 pub use apiakeylo_el1::APIAKEYLO_EL1;
 pub use apibkeyhi_el1::APIBKEYHI_EL1;
 pub use apibkeylo_el1::APIBKEYLO_EL1;
+pub use ccsidr2_el1::CCSIDR2_EL1;
 pub use ccsidr_el1::CCSIDR_EL1;
 pub use clidr_el1::CLIDR_EL1;
 pub use cntfrq_el0::CNTFRQ_EL0;
@@ -232,6 +249,7 @@ pub use far_el1::FAR_EL1;
 pub use far_el2::FAR_EL2;
 pub use far_el3::FAR_EL3;
 pub use fp::FP;
+pub use hacr_el2::HACR_EL2;
 pub use hafgrtr_el2::HAFGRTR_EL2;
 pub use hcr_el2::HCR_EL2;
 pub use hdfgrtr_el2::HDFGRTR_EL2;
@@ -276,6 +294,8 @@ pub use id_aa64dfr0_el1::ID_AA64DFR0_EL1;
 pub use id_aa64dfr1_el1::ID_AA64DFR1_EL1;
 pub use id_aa64isar0_el1::ID_AA64ISAR0_EL1;
 pub use id_aa64isar1_el1::ID_AA64ISAR1_EL1;
+pub use id_aa64isar2_el1::ID_AA64ISAR2_EL1;
+pub use id_aa64isar3_el1::ID_AA64ISAR3_EL1;
 pub use id_aa64mmfr0_el1::ID_AA64MMFR0_EL1;
 pub use id_aa64mmfr1_el1::ID_AA64MMFR1_EL1;
 pub use id_aa64mmfr2_el1::ID_AA64MMFR2_EL1;
@@ -298,6 +318,7 @@ pub use mpuir_el2::MPUIR_EL2;
 pub use mvfr0_el1::MVFR0_EL1;
 pub use mvfr1_el1::MVFR1_EL1;
 pub use mvfr2_el1::MVFR2_EL1;
+pub use osdlr_el1::OSDLR_EL1;
 pub use oslar_el1::OSLAR_EL1;
 pub use par_el1::PAR_EL1;
 pub use pmuserenr_el0::PMUSERENR_EL0;
@@ -334,6 +355,7 @@ pub use tcr_el2::TCR_EL2;
 pub use tpidr_el0::TPIDR_EL0;
 pub use tpidr_el1::TPIDR_EL1;
 pub use tpidr_el2::TPIDR_EL2;
+pub use tpidr_el3::TPIDR_EL3;
 pub use tpidrro_el0::TPIDRRO_EL0;
 pub use ttbr0_el1::TTBR0_EL1;
 pub use ttbr0_el2::TTBR0_EL2;

packages/aarch64-cpu/src/registers/accdata_el1.rs

@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2018-2026 by the author(s)
+//
+// Author(s):
+//   - Callum Thomson <callumthom11@gmail.com>
+
+//! Accelerator Data - EL1
+
+use tock_registers::interfaces::{Readable, Writeable};
+use tock_registers::register_bitfields;
+
+pub struct Reg;
+
+register_bitfields! {u64,
+    pub ACCDATA_EL1 [
+        ACCDATA OFFSET(0) NUMBITS(32) [],
+    ]
+}
+
+impl Readable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_read_raw!(u64, "ACCDATA_EL1", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_write_raw!(u64, "ACCDATA_EL1", "x");
+}
+
+pub const ACCDATA_EL1: Reg = Reg;

packages/aarch64-cpu/src/registers/actlrmask_el1.rs

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2018-2026 by the author(s)
+//
+// Author(s):
+//   - Callum Thomson <callumthom11@gmail.com>
+
+//! Auxiliary Control Masking Register - EL1
+
+use tock_registers::interfaces::{Readable, Writeable};
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_read_raw!(u64, "ACTLRMASK_EL1", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_write_raw!(u64, "ACTLRMASK_EL1", "x");
+}
+
+pub const ACTLRMASK_EL1: Reg = Reg;

packages/aarch64-cpu/src/registers/actlrmask_el2.rs

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2018-2026 by the author(s)
+//
+// Author(s):
+//   - Callum Thomson <callumthom11@gmail.com>
+
+//! Auxiliary Control Masking Register - EL2
+
+use tock_registers::interfaces::{Readable, Writeable};
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_read_raw!(u64, "ACTLRMASK_EL2", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_write_raw!(u64, "ACTLRMASK_EL2", "x");
+}
+
+pub const ACTLRMASK_EL2: Reg = Reg;

packages/aarch64-cpu/src/registers/afsr0_el2.rs

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2026 by the author(s)
+//
+// Author(s):
+//   - Callum Thomson <callumthom11@gmail.com>
+
+//! Auxiliary Fault Status Register 0 - EL2
+//!
+//! Provides IMPLEMENTATION DEFINED fault status information for synchronous aborts that are taken to EL2.
+
+use tock_registers::interfaces::{Readable, Writeable};
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_read_raw!(u64, "AFSR0_EL2", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_write_raw!(u64, "AFSR0_EL2", "x");
+}
+
+pub const AFSR0_EL2: Reg = Reg {};

packages/aarch64-cpu/src/registers/afsr0_el3.rs

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2026 by the author(s)
+//
+// Author(s):
+//   - Callum Thomson <callumthom11@gmail.com>
+
+//! Auxiliary Fault Status Register 0 - EL3
+//!
+//! Provides IMPLEMENTATION DEFINED fault status information for synchronous aborts that are taken to EL3.
+
+use tock_registers::interfaces::{Readable, Writeable};
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_read_raw!(u64, "AFSR0_EL3", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_write_raw!(u64, "AFSR0_EL3", "x");
+}
+
+pub const AFSR0_EL3: Reg = Reg {};

packages/aarch64-cpu/src/registers/ccsidr2_el1.rs

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2018-2026 by the author(s)
+//
+// Author(s):
+//   - Callum Thomson <callumthom11@gmail.com>
+
+//! Current Cache Size ID Register 2 - EL1
+
+use tock_registers::interfaces::Readable;
+use tock_registers::register_bitfields;
+
+pub struct Reg;
+
+register_bitfields! {u64,
+    pub CCSIDR2_EL1 [
+        NumSets OFFSET(0) NUMBITS(24) [],
+    ]
+}
+
+impl Readable for Reg {
+    type T = u64;
+    type R = CCSIDR2_EL1::Register;
+
+    sys_coproc_read_raw!(u64, "CCSIDR2_EL1", "x");
+}
+
+pub const CCSIDR2_EL1: Reg = Reg;

packages/aarch64-cpu/src/registers/hacr_el2.rs

@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: Apache-2.0 OR MIT
+//
+// Copyright (c) 2018-2026 by the author(s)
+//
+// Author(s):
+//   - Callum Thomson <callumthom11@gmail.com>
+
+//! Hypervisor Auxiliary Control Register - EL2
+
+use tock_registers::interfaces::{Readable, Writeable};
+
+pub struct Reg;
+
+impl Readable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_read_raw!(u64, "HACR_EL2", "x");
+}
+
+impl Writeable for Reg {
+    type T = u64;
+    type R = ();
+
+    sys_coproc_write_raw!(u64, "HACR_EL2", "x");
+}
+
+pub const HACR_EL2: Reg = Reg;

packages/aarch64-cpu/src/registers/id_aa64dfr0_el1.rs

@@ -13,6 +13,19 @@ use tock_registers::{interfaces::Readable, register_bitfields};
 
 register_bitfields! {u64,
     pub ID_AA64DFR0_EL1 [
+
+        /// Zero PMU event counters for Guest
+        HPMN0 OFFSET(60) NUMBITS(4) [
+            Unpredictable = 0b0000,
+            Defined = 0b00001,
+        ],
+
+        /// Trace Buffer External Mode Extension
+        ExtTrcBuff OFFSET(56) NUMBITS(4) [
+            NotImplemented = 0b0000,
+            Implemented = 0b00001,
+        ],
+
         /// Branch Record Buffer Extension.
         ///
         /// - 0000 Branch Record Buffer Extension not implemented.
@@ -65,15 +78,33 @@ register_bitfields! {u64,
             Implemented = 0b0001,
         ],
 
+        /// OS Double Lock implemented
+        DoubleLock OFFSET(36) NUMBITS(4) [
+            Implemented = 0b0000,
+            NotImplemented = 0b1111,
+        ],
+
         /// Statistical Profiling Extension version.
         PMSVer OFFSET(32) NUMBITS(4) [],
 
         /// Number of context-aware breakpoints, minus 1.
         CTX_CMPs OFFSET(28) NUMBITS(4) [],
 
+        /// Synchronous-exception-based event profiling
+        SEBEP OFFSET(24) NUMBITS(4) [
+            NotImplemented = 0b0000,
+            Implemented = 0b00001,
+        ],
+
         /// Number of watchpoints, minus 1.
         WRPs OFFSET(20) NUMBITS(4) [],
 
+        /// PMU Snapshot extension
+        PMSS OFFSET(16) NUMBITS(4) [
+            NotImplemented = 0b0000,
+            Implemented = 0b00001,
+        ],
+
         /// Number of breakpoints, minus 1.
         BRPs OFFSET(12) NUMBITS(4) [],