eda-playground

This repository contains VHDL implementations for all hardware design challenges (quests/questions) featured on the chipdev.io website.

Reusable HDL modules, packages, and testbench utilities for FPGA and ASIC development, supporting both VHDL and Verilog.

A VHDL code base that contains Utility Packages for both HDL and Testbenches

Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.

4-bit ALU design and simulation using Verilog HDL

4-bit ALU RTL to Gate-Level Synthesis using Yosys + ABC on EDA Playground

Multiplexer (2:1, 4:1, 8:1) designs in Verilog HDL using case, if-else & ternary styles — simulated with Icarus Verilog and synthesized with Yosys on EDA Playground.

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

SystemVerilog verification of an 8-bit × 16 synchronous FIFO using a class-based testbench, scoreboard, and 10+ SVA assertions.

SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

Implementation of 4-bit Arithmetic Logic Unit using structural modeling in Verilog. Features 8 operations controlled by 3-bit select line. Simulated on EDA Playground with waveform analysis.

5-stage MIPS pipeline CPU in Verilog with data forwarding, hazard detection and full instruction set. Simulated on EDA Playground.

UART Transmitter/Receiver in Verilog - 9600 baud, 8-bit, full loopback tested. Simulated on EDA Playground with Icarus Verilog.

Verilog HDL design & simulation of ROM, PLA, and PAL at gate-level and pseudo-NMOS transistor-level, verified in EDA Playground

Synchronous FIFO implementation in Verilog with testbench and simulation waveforms

UART communication system in Verilog featuring transmitter, receiver, baud rate generator, self-checking testbench, and comprehensive verification using EDA Playground.

Advanced VLSI Digital Clock in Verilog (RTL) featuring hardware debouncing, alarm FSM, and a real-time Python/Tkinter GUI dashboard via UART.

UART Transmitter, Receiver and Loopback implementation in Verilog

UVM extension for JSON transaction recording and waveform visualization — runs on EDA Playground or locally