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CP regfile Fmax, early-Z fix + default on, asic_gate 4x4 top/gfx, CI shards + ccache - #425

Merged

tinebp merged 8 commits into

ci-earlyz-asic-gate

Oct 6, 2026

Merged

CP regfile Fmax, early-Z fix + default on, asic_gate 4x4 top/gfx, CI shards + ccache#425
tinebp merged 8 commits into
masterfrom
ci-earlyz-asic-gate

Commits on Oct 5, 2026
- cp: decode the AXI-Lite register file flat, not as a priority chain
  
  tinebp
  and
  claude
  committed
  9e96492
- raster: carry the early-Z depth plane through the quad-evaluator stage
  
  tinebp
  and
  claude
  committed
  7518c88
- config: enable raster early-Z wherever RASTER and OM are both present
  
  tinebp
  and
  claude
  committed
  fec2224
- ci: gate asic top and gfx at NT=NW=4 and record the four new baselines
  
  tinebp
  and
  claude
  committed
  27312cb
- ci: shard long cells on recorded runtimes, 3 h timeout, ccache back on
  
  tinebp
  and
  claude
  committed
  48c9726
- ci: hold asic_gate Fmax to the target clock, not to the baseline
  
  tinebp
  and
  claude
  committed
  ba32c46
- ci: re-record the rtu asic_gate baseline after Vulkan rt (#424)
  
  tinebp
  and
  claude
  committed
  f1eb860
- ci: re-record the fpga_gate top and gfx baselines
  
  tinebp
  and
  claude
  committed
  62aaa31