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Shared cases could only drive a design through host writes and ticks, so
the SystemVerilog timing controls had no portable cases that run on the
external simulators too.
- Add `(run_until TIME)` and `(run_to_finish)` to the script language and
`run_until` / `run_to_finish` to the `Backend` contract. A case using
them is timed (`Design::timed`): the design's own processes, delays and
clocks run, and only checks may follow `run_to_finish`.
- Generate timed testbenches for Verilator and Icarus: every compiled
source gets a `1ns/1ps` time scale, the testbench counts picoseconds so
its settles stay inside one time unit, `run_until` delays to the exact
time, and the checks after `run_to_finish` run in a `final` block while
a `forever` delay keeps the simulation alive until the design finishes.
A simulator's own `$finish` notice is not design output.
- Let a `Simulation` be built on each backend
(`SimulatorBuilder<Simulation>::build_{native,cranelift,wasm,interpreter}`)
and read or write four-state values, so Celox runs timed cases on every
backend through a `Simulation`-backed adapter.
- Add the `timing` SystemVerilog group: 13 cases for `#delay`, `@(event)`,
`wait`, `always` processes, tasks with timing and four-state edges, and
refresh the retained verification reports. The Veryl suite's results are
unchanged under the new time scale.
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- Settling in the Celox timed adapter also resumes the processes a write woke (`Simulation::settle`), as the generated bench's settle step does. - `run_to_finish` keeps one late event pending instead of a perpetual one; when it comes, the run fails as unfinished and skips the final checks. - Simulator `$finish` notices are filtered only for the staged source files, not for every line of their shape. - The script's top-level bindings are module-scope variables, so the checks after `run_to_finish` see them in their `final` block. - `run_until` rejects a time above `RUN_UNTIL_LIMIT` in every adapter.
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# Conflicts: # crates/celox-test-suite/verification/sv/icarus.json # crates/celox-test-suite/verification/sv/verilator.json
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# Conflicts: # crates/celox/src/simulation.rs
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# Conflicts: # crates/celox/src/simulation.rs
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| /// time: processes waiting for it resume when the simulation next runs. | ||
| pub fn set_wide(&mut self, signal: SignalRef, value: num_bigint::BigUint) { | ||
| self.simulator.set_wide(signal, value); | ||
| self.synchronize_host_write(); |
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When either new setter drives an always_ff/edge-sensitive input in a design with no waiting processes or queued events, the default non-eager write leaves only pending_host_work; next_event_time() still requires has_waiting_processes(), so it returns None even though step() would dispatch the FF edge at the current time. An event loop driven by next_event_time() therefore stops before applying this write. Fresh evidence beyond the earlier waiter report is this FF-only path, which has no runtime waiter to satisfy that predicate; publish dirty edge work as current-time readiness and cover it with an owning-crate public-API regression.
AGENTS.md reference: AGENTS.md:L51-L53
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| @@ -0,0 +1,246 @@ | |||
| { | |||
| "cases": [ | |||
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The committed timing.vtest contains 128 cases, but this new Icarus report records only 17 of them (and the corresponding Verilator report only 13), while the checked-in matrix and summary were not updated with the remaining timed cases. Consequently the retained verification set and aggregate counts present the new timed coverage as externally validated while omitting most of the changed shared cases, including the later staging regressions; regenerate the focused reports and their indexes after running the changed adapters. This is a coverage-contract change rather than a routine evidence refresh.
AGENTS.md reference: AGENTS.md:L22-L30
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Converted to draft: superseded by the redesign in #1123 (comment). Kept as a reference implementation; it will be closed when its replacement merges. |
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Stacked on #1158, part of #1123. Shared timed SystemVerilog scripts and independent external adapters stage host inputs before executing procedures, callable continuous drivers or module-input actuals. Declaration initializers retain source order, assignment types, immediate finish and constant-initializer clock baselines. Initializer constant probes reuse packages analyzed from all prepared/preprocessed sources, preserving static clock baselines for cross-file and imported constant functions. Both public signal setters publish host work through the same helper as modify, including eager runtime-event drain settling. Ordered macro definitions flow through source emission, scale validation and top-port metadata using the actual adapter defines.
Continuous-driver temporaries preserve declared destination types and unpacked dimensions. Gated scalar input temporaries also preserve package-qualified formal typedefs, including enum identity and unpacked shape. Built-in packed inputs retain instantiated-port width, and packed instance arrays retain the actual expression's natural width for broadcast/distribution (IEEE1800-2023 23.3.3.5). A nominal shape that cannot be transported produces an emission error instead of silently becoming a vector.
Direct adapter tests cover enum input actuals, unpacked typedef input actuals, continuous enum/unpacked drivers, signed/parameterized instance arrays, staged function values, imports and macro state. The enum input example passes both installed tools before and after the type-preserving change; the unpacked input example genuinely failed before with an array/non-array connection mismatch and passes with Verilator after it. Icarus rejects that original unpacked-function-return shape. Celox's existing callable-actual limitations (#88) are tested through the external APIs without adding backend exclusions.
Validation: library217, suite unit46 plus integration/doctests, all10 live adapter integrations, formatting and affected all-target clippy pass. All128 timing cases run fresh: Icarus124 pass/4 existing ignored; Verilator126 pass/2 existing four-state limitations. New portable zero-trip dependency and three-file package-initializer regressions are registered in the Celox harness; the full timing filter passes520 checks and final stacked SV3156 passes in #1161. Public API setter tests check actual process resumption with/without a concurrent drain and intervening reads/evaluation on all four backends. Retained verification files, proof manifests and exclusions are unchanged. Latest-head CI must finish before merge.